3D Memory Gate Structure for Thin Channels and Field Reliability
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Solution Overview
Problem
The challenge in semiconductor memory devices is to maintain high integration and miniaturization while ensuring effective performance and reliability, particularly in reducing the thickness of semiconductor layers without compromising cell channel width and enhancing field reliability.
Innovation Solution
The semiconductor memory device design includes alternately stacked insulation and semiconductor layers with gate electrodes that overlap both layers, featuring a fin shape for the semiconductor layers and a recessed, rounded contact surface, which increases the connected area and reduces thickness while maintaining cell channel width, and utilizes offset and zigzag arrangements of gate electrodes to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of semiconductor layers is reduced to achieve miniaturization, then the degree of integration is improved, but the cell channel width may be compromised and field reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D structures to vertical 3D structures by stacking multiple insulation layers and semiconductor layers alternately in the vertical direction. This dimensional change allows the device to achieve miniaturization in the horizontal plane while maintaining functional performance through vertical stacking, effectively resolving the contradiction between reduced thickness and maintained reliability.
Solution Approach 2:
The patent implements a nested structure where charge storage layers are positioned between insulation layers, which are in turn surrounded by gate electrodes. Multiple such nested units are stacked vertically, creating a compact configuration that maintains adequate cell channel width while reducing overall device thickness, thereby preserving field reliability during miniaturization.
2Reliability
If gate electrodes are arranged in offset and zigzag patterns, then coupling between charge storage layers is reduced, but device complexity increases
Solution Approach 1:
The patent employs asymmetric offset arrangements where adjacent gate electrodes are deliberately misaligned in the horizontal direction, creating a zigzag pattern when viewed from above. This asymmetric configuration effectively reduces capacitive coupling between charge storage layers while the systematic nature of the offset pattern keeps manufacturing complexity manageable through standardized fabrication processes.
Data Source
AI summary
A semiconductor memory device includes structures including insulation layers and semiconductor layers alternately stacked in a vertical direction, the structures being spaced apart from one another in a horizontal direction; an interlayer insulation layer between the structures; gate electrodes respectively in gate trenches passing through the interlayer insulation layer in the vertical direction, between the structures, the gate electrodes connected to the semiconductor layers; and vertical insulation layers respectively on sidewalls of the gate trenches, wherein each gate electrode includes first portions overlapping the insulation layers in the horizontal direction and second portions overlapping the semiconductor layers in the horizontal direction, and a first width of each first portion in the horizontal direction is greater than a second width of each second portion in the horizontal direction.