3D Memory Gate Electrode Uniformity via Dummy Source Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing 3D memory device fabrication processes face challenges with gate-replacement in staircase regions, leading to unevenly filled gate electrodes, high resistance, and nonuniform dummy channel holes due to large gate line slits, which result in performance variations and wafer warpage issues.
Innovation Solution
The introduction of dummy source structures distributed within the staircase region, with insulating spacer layers and conductive contacts, replaces the traditional gate line slits, allowing for uniform etching and improved conductive material deposition, reducing resistivity and warpage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional gate line slits are used in staircase regions, then fabrication process is simpler, but gate electrodes become unevenly filled with high resistance and dummy channel holes become nonuniform
Solution Approach 1:
The staircase region is divided into multiple segments with different structures: actual memory cells in the first region and dummy source structures with insulating spacer layers and conductive contacts in the second region. This segmentation allows each region to be optimized independently, achieving uniform gate electrodes in memory regions while managing the complex staircase geometry through structured dummy regions.
Solution Approach 2:
Different structural qualities are applied to different locations within the staircase region. The first region contains actual memory cells with standard structures, while the second region contains dummy source structures with insulating spacer layers and conductive contacts. This local differentiation resolves the uniformity issue by providing location-specific structures that address local fabrication challenges.
2Ease of manufacture
If large gate line slits are used, then etching process is easier, but resistivity increases and warpage issues occur
Solution Approach 1:
Insulating spacer layers are introduced as intermediary structures between the conductive layers and the staircase structure. These spacer layers mediate the interaction between the conductive material and the underlying structure, enabling better control over material deposition and reducing warpage while maintaining etching feasibility through the structured dummy source regions.
3Manufacturing precision
If dummy source structures with insulating spacer layers are introduced, then uniformity and quality of gate electrodes improve, but fabrication process complexity increases
Solution Approach 1:
The insulating spacer layers are formed preliminarily before the conductive layers are deposited. This preliminary action of creating the spacer structure first allows for controlled and uniform deposition of subsequent conductive materials, ensuring high uniformity of gate electrodes while organizing the fabrication process into manageable sequential steps that reduce overall process complexity.
Data Source
AI summary
Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.