3D Memory Array Strings With Gate-Last Metal Line Coupling

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Solution Overview

Problem

Existing memory array fabrication methods face challenges in forming vertically-stacked memory cells with precise control over conductor and insulative layers, leading to potential etching issues and structural integrity problems.

Innovation Solution

A method involving 'gate-last' processing is employed, where conductor and insulative tiers are formed with precise control, using anisotropic etching to create vertically-stacked memory cells, and metal silicide or elemental-form metal lines are used to enhance structural integrity and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used to form vertically-stacked memory cells, then manufacturing process simplicity is maintained, but manufacturing precision and structural integrity deteriorate due to poor control over conductor and insulative layers

Engineering Contradiction:

Improvecontrol over conductor and insulative layersVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into distinct sequential steps: forming conductor tiers, forming insulative tiers, forming channel-material strings, and selective isotropic etching. Each step builds upon the previous one, allowing precise control over the vertical stack structure while maintaining a systematic approach to manufacturing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Conductor tiers and insulative tiers are formed in advance before the channel-material strings are introduced. This preliminary formation of the tiered structure enables subsequent precise etching and assembly operations, ensuring proper alignment and structural integrity of the vertically-stacked memory cells

Inventive Principle:

Principle #10Preliminary action

2Stability of the object's composition

If vertically-stacked memory cells are formed with precise layer control, then structural integrity is improved, but etching issues and manufacturing complexity increase

Engineering Contradiction:

Improvestructural integrity of vertically-stacked cellsVSAvoidfabrication ease

Core Design Contradiction:

Stability of the object's compositionVSEase of manufacture

Solution Approach 1:

sacrificial material is introduced as an intermediary element during fabrication. This material is formed between conductor tiers, serves as a placeholder that facilitates precise isotropic etching of channel-material strings, and is later removed to create the desired structure without directly etching conductor materials

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The etching process uses selective parameters: isotropic etching is applied to remove sacrificial material and expose channel-material strings, while the conductor tiers remain intact due to their different material composition. This parameter differentiation enables precise structural formation without cross-contamination

Inventive Principle:

Principle #35Parameter changes

3Reliability

If metal silicide or elemental-form metal lines are used, then electrical connectivity is enhanced, but device complexity increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Metal silicide or elemental-form metal lines are selectively applied in specific locations within the conductor tiers where enhanced electrical connectivity is required. This localized application improves connectivity at critical interfaces without unnecessarily complicating the entire device structure

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures robust and efficient formation of vertically-stacked memory cells with improved structural integrity and electrical connectivity, facilitating the fabrication of high-performance memory arrays.

Implementation Method 1

using anisotropic etching to create vertically-stacked memory cells

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

The sacrificial material is isotropically etched from the lowest first tier through the horizontally-elongated trenches

Methodology Applied

Scientific EffectIsotropic etching:

Data Source

PatentUS12453089B2Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Publication Date: 2025.10.21 LODESTAR LICENSING GROUP LLC

AI summary

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.