3D Memory Cell Layout With Source-Line-First GIDL Control
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in manufacturing complexity and operational reliability compared to two-dimensional devices.
Innovation Solution
The semiconductor memory device incorporates a common source line, a channel structure with a hollow-type channel layer, and a gate stack structure with interlayer insulating layers and conductive patterns alternately stacked, along with a bit line connected to the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cells are arranged to improve degree of integration, then storage capacity increases, but manufacturing complexity and operational reliability deteriorate
Solution Approach 1:
The channel structure is divided into multiple discrete channel holes penetrating through stacked gate electrodes, allowing independent formation and control of each memory cell unit. This segmentation enables modular manufacturing where each cell can be processed separately, reducing overall manufacturing complexity while maintaining high storage capacity through vertical stacking
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked cells with channel holes extending through multiple gate layers. This dimensional change increases storage capacity by utilizing the vertical dimension, while the regular repeating pattern of the stacked structure enables standardized manufacturing processes that control complexity
2Quantity of substance
If three-dimensional memory cells are arranged to improve degree of integration, then storage capacity increases, but operational reliability deteriorates
Solution Approach 1:
The junction overlap region is specifically engineered with localized doping to create an electric field that suppresses GIDL current. By concentrating the reliability-enhancing feature at the critical junction overlap region rather than throughout the entire device, the patent improves operational reliability without adding complexity to other parts of the structure
Solution Approach 2:
The junction overlap region is designed in advance to generate an electric field that counteracts the harmful GIDL current before it can cause reliability issues. This preliminary anti-action is built into the device structure itself, proactively preventing operational failures rather than relying on post-manufacturing corrections
3Quantity of substance
If conventional three-dimensional structures are used, then storage capacity increases, but GIDL current increases reducing operational reliability
Solution Approach 1:
The patent introduces a specialized junction overlap region with localized doping exactly where needed to suppress GIDL current. This local quality enhancement creates a beneficial electric field at the critical interface between channel and gate, reducing the harmful GIDL effect without requiring changes to the overall three-dimensional stacked structure that enables high storage capacity
Solution Approach 2:
The patent converts the potentially harmful junction region that generates GIDL current into a beneficial structure by creating a controlled junction overlap region. The doping in this region generates an electric field that, rather than allowing harmful leakage, actively suppresses GIDL current, turning a weakness into a strength while maintaining the high-capacity three-dimensional architecture
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.