3D Memory Channel Structure for Stable GIDL Erase Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reliability of 3D semiconductor memory devices is compromised as the number of stacked memory cells increases, leading to degraded operational performance.
Innovation Solution
A semiconductor memory device design featuring alternately stacked interlayer insulating layers and conductive patterns, with channel structures that include a channel layer extending to the uppermost conductive pattern, a memory layer surrounding the channel layer, and a doped semiconductor pattern above the channel layer, along with a manufacturing method that forms these structures to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to improve integration level, then the area occupied by memory cells per unit area is reduced, but the reliability of operation is degraded
Solution Approach 1:
The patent applies local quality by creating a protrusion at a specific location on the channel layer (where it contacts the memory layer) to locally enhance the electric field distribution. This localized structural modification stabilizes the GIDL current specifically at the critical interface region, thereby improving operational reliability without reducing the number of stacked memory cells. The protrusion creates a controlled high-field region that prevents excessive carrier generation and stabilizes erase operation.
Solution Approach 2:
The patent changes the geometric parameter of the channel layer by adding a protrusion that extends into the memory layer. This parameter change modifies the electric field distribution and charge transport characteristics, stabilizing the GIDL current during erase operations. The protrusion height and position are carefully controlled to optimize the balance between maintaining low integration level and ensuring high operational reliability.
2Area of stationary object
If the number of stacked memory cells is increased to reduce area per unit area, then device density is improved, but GIDL current stability is degraded
Solution Approach 1:
The protrusion structure creates a localized high-field region at the channel-memory layer interface, which stabilizes charge transport and prevents excessive carrier generation. This local modification ensures stable GIDL current characteristics even when multiple memory cells are stacked vertically, thereby maintaining erase operation reliability while achieving high device density.
Solution Approach 2:
The patent introduces a vertical dimension to the channel layer structure by creating a protrusion that extends downward into the memory layer. This three-dimensional structural modification changes the electric field distribution from a planar configuration to a concentrated vertical field at the interface, stabilizing charge transport mechanisms and GIDL current across stacked memory cells.
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.