3D Semiconductor Memory With Conductive Pad For GIDL Erase
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration density due to the high cost and complexity of forming fine patterns, necessitating the development of three-dimensional semiconductor memory devices with improved electrical characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure of gate electrodes, including a ground selection gate, cell gate, string selection gate, and erase gate, vertically arranged on a substrate, along with a conductive pad within the vertical channel, facilitating efficient gate-induced drain leakage (GIDL) during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple gate electrodes (first erase gate, second erase gate, cell gate, string selection gate) are stacked vertically to form a 3D architecture, enabling higher integration density without requiring finer lateral patterning. The vertical channel penetrates through multiple gate layers, creating a three-dimensional transistor structure that overcomes the limitations of 2D scaling.
2Quantity of substance
If three-dimensional semiconductor memory devices are designed with multiple gate electrodes stacked vertically, then integration density is improved, but device structure complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functionally distinct gate electrodes stacked vertically: first erase gate electrode, second erase gate electrode, cell gate electrode, and string selection gate electrode. Each segment performs a specific function (erase operations at different levels, cell control, string selection), allowing complex functionality to be achieved through modular vertical stacking rather than complex lateral interconnections.
Solution Approach 2:
The vertical channel structure serves multiple functions simultaneously: it acts as the conductive path for memory cells, provides the structural framework for stacking multiple gates, and enables both cell operations and erase operations through different gate controls. The shared vertical channel reduces overall device complexity by consolidating multiple functions into a single structural element.
3Reliability
If conductive pad is positioned at the same vertical level as erase gate electrode, then GIDL phenomenon is enhanced for efficient erase operation, but manufacturing precision requirements increase
Solution Approach 1:
The conductive pad acts as an intermediary element that facilitates the GIDL phenomenon during erase operations. By positioning the conductive pad at the same vertical level as the first erase gate electrode, it creates an optimal electric field configuration that enhances hole generation and supply to the charge storage layer. This intermediary structure enables efficient erase functionality while providing a defined geometric reference that can simplify alignment requirements compared to direct gate-to-channel configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves enhanced integration density and improved electrical characteristics by enabling effective GIDL phenomenon, allowing for efficient hole supply to the charge storage layer, thereby optimizing the erase operation of the 3D semiconductor memory device.
Implementation Method 1
facilitating efficient gate-induced drain leakage (GIDL) during erase operations
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.