3D Memory Stack Structure for Stable GIDL During Erase
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high operational reliability and large capacity while maintaining portability, particularly in three-dimensional designs where dopant diffusion and process errors in junction overlap regions can lead to unstable gate-induced drain leakage currents during erase operations.
Innovation Solution
The semiconductor memory device incorporates a stack structure with etch stop layers and a source layer, where the etch stop layers are made of insulating materials like SiCO and SiCN, limiting dopant diffusion to the surface contact between the channel and source layers, and a manufacturing method that forms channel structures penetrating these layers to reduce process errors and ensure stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory device structure is adopted to increase capacity, then storage capacity is improved, but dopant diffusion and process errors in junction overlap regions increase leading to unstable gate-induced drain leakage currents
Solution Approach 1:
An etch stop layer is introduced as an intermediary component between the source layer and the channel structure. This etch stop layer acts as a mediator that prevents dopant diffusion into the channel region while maintaining the three-dimensional structure. The etch stop layer has specific etch selectivity that allows it to stop the dopant diffusion process, thereby stabilizing the gate-induced drain leakage current during erase operations while preserving the high capacity three-dimensional architecture.
2Reliability
If etch stop layers are added to control dopant diffusion, then reliability is improved, but device complexity increases
Solution Approach 1:
The device structure is segmented into distinct functional layers with the etch stop layer being a separate, dedicated component. This segmentation allows the etch stop layer to perform its specific function of controlling dopant diffusion without interfering with other device operations. The segmented structure with clear functional separation improves reliability through better dopant confinement while managing complexity through modular design where each layer has a specific purpose.
Solution Approach 2:
The etch stop layer serves multiple functions: it acts as a diffusion barrier to control dopant movement, provides an etch stop reference for manufacturing processes due to its selective etching properties, and maintains the structural integrity of the three-dimensional device. This multi-functionality justifies the added layer by providing several benefits simultaneously, thereby improving reliability without proportionally increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the semiconductor memory device by reducing dopant diffusion distance and process errors, thereby stabilizing gate-induced drain leakage currents during erase operations and ensuring reliable data storage.
Implementation Method 1
a material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.