3D Memory Ground Via Structure for Charge Dissipation

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Solution Overview

Problem

In 3D flash memory manufacturing, the non-uniform thickness of patterned hard mask layers leads to charge accumulation and arcing issues, causing damage to substrates and devices due to the beveled profile of the substrate edges.

Innovation Solution

A semiconductor structure with a through via connected to the ground layer in the dielectric stacked structure, which forms a conductive path to dissipate charges, preventing arcing by ensuring the charges are transmitted to the substrate through this path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the patterned hard mask layer is extended to the sidewall of the stacked structure to cover the beveled profile, then the coverage is improved, but the thickness uniformity deteriorates and charge accumulation occurs

Engineering Contradiction:
Improvecoverage area of hard mask layerVSAvoidthickness uniformity of hard mask layer
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

A ground layer is introduced as an intermediary conductive structure between the substrate and the dielectric stacked structure. This ground layer provides a charge dissipation path that prevents charge accumulation during etching processes, allowing the hard mask layer to be extended onto sidewalls without causing arcing damage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The ground layer is formed on the substrate before the dielectric stacked structure is built. This preliminary conductive structure is prepared in advance to establish charge dissipation pathways before any etching operations that might generate charges, preventing arcing issues from the outset.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If charges are allowed to accumulate during deep-etching to maintain process stability, then the etching uniformity is improved, but arcing occurs causing damage to substrate and devices

Engineering Contradiction:
Improveetching process stabilityVSAvoidarcing damage to substrate and devices
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The ground layer converts the harmful charge accumulation into a beneficial feature by providing a controlled discharge path. Instead of allowing charges to build up to dangerous levels that cause uncontrolled arcing, the ground layer guides charges to dissipate safely, transforming a potential damage source into a process-stabilizing mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents arcing and subsequent damage to substrates and devices by ensuring charges are safely dissipated, maintaining the integrity of the semiconductor structure during the formation of vertical channel holes.

Implementation Method 1

the through via is disposed in the dielectric stacked structure and connected to the ground layer to release the charges generated in the process

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20240258250A1Semiconductor structure for 3D memory and manufacturing method thereof
Publication Date: 2024.08.01 MACRONIX INTERNATIONAL CO LTD
  • US20240258250A1 patent drawing
  • US20240258250A1 patent drawing
  • US20240258250A1 patent drawing

AI summary

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a dielectric layer disposed on a substrate, a ground layer, a ground via, a dielectric stacked structure, and a through via. The ground layer is disposed on the dielectric layer. The ground via is disposed in the ground layer and the dielectric layer and electrically connected to the substrate. The dielectric stacked structure is disposed on the ground layer. The through via is disposed in the dielectric stacked structure and connected to the ground layer. The dielectric stacked structure has a vertical channel hole.