3D Semiconductor Memory Stack With Grounded Penetration Contacts
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to expensive equipment needed for fine pattern formation, hindering increased data storage capacity and performance, prompting the development of three-dimensional semiconductor memory devices with vertically arranged memory cells.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure including interlayer dielectric layers and gate electrodes alternately stacked, featuring penetration contacts with widths decreasing from the substrate, and a second substrate grounded through a penetration contact to prevent arcing, enhancing reliability and electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional or planar semiconductor devices are used, then the fabrication process is relatively simple, but integration is greatly influenced by the level of fine pattern forming technology and cannot be increased further due to expensive process equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. The memory cells are arranged in multiple layers with stack structures containing alternating interlayer dielectric layers and gate electrodes, enabling increased storage capacity by utilizing the vertical dimension rather than being constrained to a single plane.
Solution Approach 2:
The three-dimensional memory device is divided into separate peripheral circuit structure and cell array structure that are bonded together through bonding pads. This segmentation allows independent optimization of each structure and simplifies the fabrication process by enabling separate manufacturing before final assembly.
2Productivity
If three-dimensional semiconductor memory devices with vertically arranged memory cells are implemented, then data storage capacity per unit area is increased, but fabrication process complexity increases
Solution Approach 1:
The device is segmented into a peripheral circuit structure and a cell array structure that are fabricated separately and then bonded together. This allows the complex three-dimensional cell array to be manufactured independently using optimized processes, while the peripheral circuits can be fabricated using standard processes, reducing overall manufacturing complexity.
Solution Approach 2:
The peripheral circuit structure and cell array structure are prepared in advance with bonding pads formed on their respective surfaces before being bonded together. This preliminary preparation of bonding interfaces simplifies the final assembly process and enables independent optimization of each structure's fabrication process.
3Reliability
If penetration contacts with decreasing widths are used, then reliability is improved by preventing arcing, but manufacturing precision requirements increase
Solution Approach 1:
The penetration contacts are designed with asymmetric width profiles, being wider at the bottom and narrower at the top. This asymmetric geometry prevents arcing by maintaining adequate contact area at the bottom while reducing the opening at the top for better insulation. The width decreases from the first substrate toward the second substrate, optimizing both reliability and manufacturability.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.