3D Memory Ground Selection Transistor Threshold Compensation
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges with disturbances and decreased cell current due to variations in threshold voltages of ground selection transistors, which are influenced by channel hole shapes and placements during manufacturing, affecting the reliability and performance of nonvolatile memory devices.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a cell array on one substrate and a peripheral circuit on another, with insulating and gate patterns stacked alternately, including a first non-programmable ground selection transistor and a second programmable ground selection transistor, where the threshold voltage of the second transistor is set based on the characteristics of the first, to maintain consistent operating conditions and compensate for defects in the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ground selection transistors are configured with channel holes in three-dimensional array structure, then degree of integration is improved, but threshold voltage distribution widens causing disturbance and decreased cell current
Solution Approach 1:
The ground selection transistor is divided into two separate transistors: a first ground selection transistor (GST1) that is not programmable and a second ground selection transistor (GST2) that is programmable. This segmentation allows each transistor to perform a specific function - GST1 provides stable reference characteristics while GST2 can be programmed to compensate for threshold voltage variations, thereby resolving the contradiction between high integration and threshold voltage consistency.
Solution Approach 2:
The patent changes the operational parameters of the ground selection transistors by making one programmable and the other non-programmable. The programmable GST2 can have its threshold voltage adjusted through programming to match the characteristics of GST1, compensating for manufacturing variations and maintaining consistent operating conditions across all memory cells.
2Ease of manufacture
If ground selection transistors are configured with varied channel hole shapes and placements, then manufacturing flexibility is improved, but cell current stability deteriorates
Solution Approach 1:
By making the second ground selection transistor programmable, the patent allows post-manufacturing adjustment of threshold voltage parameters. This compensates for variations caused by different channel hole shapes and placements, maintaining cell current stability despite manufacturing flexibility in channel hole configuration.
3Device complexity
If single ground selection transistor is used, then device complexity is reduced, but operating feature consistency deteriorates
Solution Approach 1:
The ground selection function is segmented into two transistors with different programmability characteristics. This segmentation, while increasing device complexity, achieves better operating feature consistency by allowing one transistor to be programmed to match the characteristics of the other, compensating for manufacturing variations.
Solution Approach 2:
The programmable second ground selection transistor acts as a feedback mechanism to compensate for threshold voltage variations. By programming GST2 to match GST1's characteristics, the system creates a self-correcting mechanism that maintains operating feature consistency across all memory cells.
Data Source
AI summary
Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.