3D Memory Stack Hard Mask Patterning for Word Line Integrity
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Solution Overview
Problem
Manufacturing 3D semiconductor memory devices with a complex circuit structure is challenging due to defects such as word line opens and pattern failures, necessitating improved manufacturing methods.
Innovation Solution
A method involving the formation of a semiconductor device with a 3D architecture using a stack assembly of dielectric and sacrificial layers, followed by selective etching and replacement with conductive regions, and the use of a hard mask layer to define precise features, enabling the creation of a 3D NOR flash device with TFTs arranged in three directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D architecture is used to increase memory capacity, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into multiple sequential patterning steps (first pattern, second pattern, third pattern) that progressively form the 3D structure. Each step creates specific features (trenches, pillars, word lines) independently, breaking down the complex 3D fabrication into manageable 2D steps that reduce manufacturing difficulty while achieving high memory capacity
Solution Approach 2:
The patent transitions from 2D planar memory architecture to 3D vertical architecture by forming stacked structures with word lines extending in multiple directions (X, Y, Z axes). This dimensional transition increases memory capacity per unit area while the segmented patterning approach manages the associated manufacturing complexity
2Manufacturing precision
If selective etching and replacement processes are used to create precise features, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
Sacrificial layers are deposited and patterned in advance before the final conductive features are formed. These sacrificial structures (including oxide layers and nitride layers) serve as temporary templates that guide subsequent etching processes, ensuring precise feature formation while simplifying the overall process by pre-establishing the geometric framework
Solution Approach 2:
Sacrificial materials act as intermediary elements between the patterning steps and final conductive feature formation. These intermediaries are selectively removed and replaced with conductive materials, enabling precise feature definition without directly exposing the conductive layers to complex patterning processes, thus improving precision while managing complexity
Data Source
AI summary
A semiconductor device includes an underlying substrate, two stack units disposed over the underlying substrate, and a feature disposed between the stack units. The stack units are spaced apart from each other. Each of the stack units includes a plurality of conductive films and a plurality of dielectric films disposed to alternate with the conductive films, an inter-metal dielectric (IMD) portion, and a hard mask film. An uppermost one of the dielectric films of each of the stack units is disposed over the conductive films, and has a dimension smaller than those of the conductive films and those of remaining ones of the dielectric films of each of the stack units. The feature includes a plurality of repeating units and a plurality of separators which are disposed to alternate with the repeating units. A method for manufacturing the semiconductor device is also disclosed.