3D Memory Staircase Structure With Single-Pattern Hole Alignment
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Solution Overview
Problem
The fabrication processes of multiple-stack 3D NAND memory devices are time-consuming and costly due to the need for multiple photomasks and high precision control in forming semiconductor channels and supporting pillars, which can lead to film quality defects and inconsistent hole dimensions.
Innovation Solution
A simplified fabrication method that uses a single staircase-forming patterning process to form multiple-stack staircase structures, reducing the number of photomasks and etching steps, and aligns pillar holes and channel holes through the structure to ensure aligned sidewalls and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks and high precision control are used to form semiconductor channels and supporting pillars, then manufacturing precision is improved, but device complexity and fabrication time increase
Solution Approach 1:
The patent combines the formation of semiconductor channels and supporting pillars into a single etching process using one photomask. The etching conditions are optimized to etch channel holes and pillar holes at different rates, allowing both structures to be formed simultaneously with consistent dimensions without requiring multiple photomasks or separate etching steps.
Solution Approach 2:
The patent changes etching parameters (such as etchant composition, temperature, or power) to create selective etching rates between channel holes and pillar holes. By controlling the etching rate difference, both hole types achieve consistent dimensions from a single pattern, resolving the contradiction between precision and process complexity.
2Manufacturing precision
If multiple photomasks and etching steps are used, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple etching steps into a single etching process that forms both channel holes and pillar holes simultaneously. This reduces the total number of fabrication steps while maintaining consistent hole dimensions through controlled etching rate differences, thereby improving productivity without sacrificing precision.
Solution Approach 2:
The patent implements a continuous etching process that forms both channel and pillar structures in one uninterrupted step. The etching conditions are maintained throughout the process to ensure consistent quality across all holes while eliminating the need for intermediate steps, thus enhancing both productivity and film quality consistency.
3Manufacturing precision
If separate fabrication processes are used for semiconductor channels and supporting pillars, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent combines the patterning and etching of semiconductor channels and supporting pillars into a single process step using one photomask. The etching parameters are tuned to achieve different etching rates for channel and pillar regions, allowing both structures to be formed with consistent patterns in one operation, eliminating time loss from multiple separate processes.
Data Source
AI summary
In an example, a method of forming a memory device includes: forming a first dielectric stack including alternately stacked first material layers and second material layers; forming a first sub-channel hole extending through the first dielectric stack in a core array region; forming a second dielectric stack including alternately stacked the first material layers and the second material layers over the first dielectric stack after the formation of the first sub-channel hole; and forming a multiple-stack staircase structure including staircases in a staircase region adjacent to the core array region after the formation of the second dielectric stack.