3D Memory Cell Layout With Horizontal Channels for Dense DRAM
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Solution Overview
Problem
Conventional memory devices face limitations in manufacturability and packing density, particularly in DRAM devices with vertically oriented memory cells, which hinder the practical stacking of memory cells due to lithography constraints and manufacturing complexity.
Innovation Solution
The development of a three-dimensional memory array with horizontally arranged transistors and capacitors, utilizing selective cavity etches and photolithographic patterning to create uniformly deposited stacks, allowing for increased packing density and reduced integration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged vertically in conventional DRAM devices, then read/write speed is maintained, but packing density and manufacturability are limited
Solution Approach 1:
The patent transitions from vertical stacking to horizontal arrangement of memory cells within a planar structure. Memory cells are organized in a three-dimensional array where transistors and capacitors are horizontally positioned, enabling increased packing density without the manufacturing complexity associated with vertical stacking. This dimensional reconfiguration allows uniform deposition techniques to be applied effectively.
Solution Approach 2:
The memory array is divided into uniformly deposited stacks that can be manufactured using standard lithography and deposition processes. Each stack contains segmented components (transistors and capacitors) arranged horizontally, allowing independent optimization of each segment while maintaining overall high density and manufacturability.
2Quantity of substance
If vertical stacking is used to increase density, then packing density improves, but lithography constraints and alignment tolerances worsen
Solution Approach 1:
By reconfiguring memory cells from vertical to horizontal arrangement, the patent eliminates the need for precise vertical alignment between stacked layers. The horizontal orientation allows components to be positioned within the same lithographic plane, significantly reducing alignment tolerance requirements and relaxing lithography constraints while maintaining high packing density.
3Ease of manufacture
If conventional vertical DRAM structure is used, then manufacturing process is simpler, but packing density is reduced
Solution Approach 1:
The patent segments the memory array into uniformly deposited stacks with horizontally arranged components. This segmentation allows each stack to be manufactured using standard, well-established deposition and lithography processes, maintaining ease of manufacture. Simultaneously, the horizontal arrangement within each stack enables increased packing density by efficiently utilizing the available planar space.
Data Source
AI summary
Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.