3D Semiconductor Memory Device Horizontal Insulating Layers
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to expensive process equipment required for fine pattern formation, hindering increased integration and performance while three-dimensional semiconductor memory devices offer improved integration but require advanced electrode and insulating layer structures to enhance electric characteristics.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a substrate with a cell array region, connection region, and electrode structure with sequentially stacked electrodes, interlayer insulating layers, and horizontal insulating layers with improved etch resistance, including a first and second horizontal insulating layer with higher concentrations of nonmetallic elements, which extend along electrodes and penetrate through the upper insulating layer to enhance electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation technology to increase integration, then integration density improves, but process equipment cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the need for expensive fine pattern formation equipment.
2Reliability
If three-dimensional semiconductor memory devices are designed with complex electrode and insulating layer structures to enhance electric characteristics, then electric performance improves, but device complexity increases
Solution Approach 1:
The patent introduces horizontal insulating layers with different etch resistance properties at specific locations within the insulating layer stack. The first horizontal insulating layer has higher etch resistance than the second horizontal insulating layer, allowing selective etching processes to form contact holes through specific regions while protecting other regions. This local differentiation of material properties enhances electric characteristics without requiring overall structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electric characteristics and prevents short circuits, allowing for increased integration and performance while reducing costs associated with advanced equipment, thereby addressing the limitations of two-dimensional devices.
Implementation Method 1
The first horizontal insulating layer may include a material having a higher etch resistance than the upper insulating layer
Implementation Method 2
A concentration of a nonmetallic element, except for oxygen, may be higher in the second horizontal insulating layer than in the upper insulating layer
Data Source
AI summary
A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.