3D Semiconductor Memory Device Horizontal Pattern Division
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the cost and practical constraints of fine pattern formation, necessitating the development of three-dimensional semiconductor memory devices with enhanced integration capabilities.
Innovation Solution
A three-dimensional semiconductor memory device is designed with horizontal patterns on a peripheral circuit structure, separated by a division structure and an etch stop pattern, and connected via penetration plugs, allowing for increased integration density and reduced process failures during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed over active regions. This dimensional transition enables significantly higher integration density while maintaining manufacturing feasibility through established semiconductor fabrication processes adapted for 3D structures.
2Quantity of substance
If three-dimensional vertically stacked memory structures are implemented, then integration density increases, but process complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple discrete memory cell layers stacked vertically. Each layer is formed over separate active regions and can be independently processed to some extent. The segmentation allows complex 3D structures to be built through repeated application of standardized fabrication steps, reducing overall process complexity while maintaining high integration density.
Solution Approach 2:
The patent employs preliminary formation of interlayer insulating films, division structures, and conductor patterns before stacking memory cell layers. These preliminary structures are prepared in advance and then used as templates or guides for subsequent memory cell formation. This preliminary action simplifies the overall manufacturing process by establishing a structured framework that guides the complex 3D assembly process.
3Quantity of substance
If fine pattern formation is used to increase integration in two-dimensional devices, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
Instead of achieving higher integration density through finer lateral patterning in the two-dimensional plane, the patent achieves density improvement by stacking multiple memory cell layers vertically. This approach utilizes the third dimension (vertical direction) to multiply storage capacity without requiring proportionally finer lateral pattern formation, thereby avoiding the exponential cost increase associated with advanced lithography processes.
Solution Approach 2:
The patent forms preliminary interlayer insulating films and division structures with relatively relaxed dimensional requirements before building the memory cell layers. These preliminary structures serve as templates that guide subsequent memory formation, allowing standard lithography processes to be used rather than requiring cutting-edge fine pattern formation, thus controlling manufacturing costs while achieving high integration density.
4Reliability
If division structures are added to separate adjacent memory structures, then manufacturing reliability improves, but device complexity increases
Solution Approach 1:
The patent introduces division structures as intermediary elements that physically separate adjacent memory structures and prevent electrical interference between them. These division structures act as mediators that isolate neighboring memory cells while maintaining the overall compact 3D architecture. The intermediary structures are integrated into the fabrication process through standard deposition and etching steps, adding minimal structural complexity while significantly improving manufacturing reliability and preventing process failures.
Data Source
AI summary
A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure.