3D Memory Horizontal Word Line Structure for Lower Resistance

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Solution Overview

Problem

The miniaturization of three-dimensional memory structures, such as DRAM, poses challenges in fabrication processes and yield due to increased resistance in vertical word line structures, which negatively affects electrical properties.

Innovation Solution

A method involving the alternately stacking of first and second semiconductor layers, etching to form isolation trenches, and depositing a conductive layer along openings using atomic layer deposition to create a horizontal word line structure, simplifying fabrication and increasing yield while reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If vertical word line structure is used in miniaturized memory, then memory density is improved, but resistance increases and electrical properties deteriorate

Engineering Contradiction:
Improvememory densityVSAvoidelectrical properties
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent inverts the conventional vertical word line structure to a horizontal word line structure. Instead of extending word lines vertically through stacked memory layers, the conductive layers are formed horizontally along the channel regions, wrapping around them. This inversion reduces the resistance path while maintaining high memory density through the stacked architecture.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from a primarily vertical word line arrangement to a horizontal configuration by depositing conductive layers that wrap around channel regions in the lateral direction. This dimensional change allows current to flow horizontally through the stacked memory structure, reducing resistance while preserving vertical stacking for high density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If miniaturization of memory structure is pursued, then memory density is improved, but fabrication complexity and yield challenges increase

Engineering Contradiction:
Improvememory densityVSAvoidfabrication complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the formation of word lines and channel region protection into a single conductive layer deposition step. The conductive layer is deposited to wrap around channel regions and form horizontal word lines simultaneously, eliminating separate fabrication steps for vertical word lines and reducing overall process complexity despite miniaturization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive layer deposition process self-organizes to wrap around the channel regions automatically, forming both the word line structure and protecting the channel regions in one step. This self-service approach simplifies fabrication by eliminating the need for separate alignment and formation steps that would increase complexity in miniaturized structures.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the fabrication processes, increases the yield of three-dimensional memory, and improves electrical properties by reducing resistance through the formation of a horizontal word line structure.

Implementation Method 1

depositing a conductive layer along the plurality of first openings by means of an atomic layer deposition process

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Data Source

PatentUS20230371231A1Three-dimensional memory and formation method thereof
Publication Date: 2023.11.16 CHANGXIN MEMORY TECH INC
  • US20230371231A1 patent drawing
  • US20230371231A1 patent drawing
  • US20230371231A1 patent drawing

AI summary

A method for forming a three-dimensional memory provided by embodiments includes: forming a substrate and a stacked layer, where the stacked layer includes first semiconductor layers and second semiconductor layers alternately stacked, a thickness of the second semiconductor layers is D1, the first semiconductor layers include a plurality of channel regions as well as a first region and a second region arranged on opposite two sides of each of the plurality of channel regions along a first direction, and the first direction is a direction parallel to the top surface of the substrate; forming a plurality of first openings respectively exposing the plurality of channel regions, a gap between adjacent two of the plurality of first openings along a second direction has a width D2, D1>D2; and depositing a conductive layer along the plurality of first openings.