3D Memory Stack With Monocrystalline Channels for Low Wiring Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the field of Integrated Circuits (ICs) is the stagnation of memory capacity and performance gains due to wire degradation with scaling, leading to high energy costs and latency in memory fetches, while current 3D memory technologies face limitations in using poly-silicon channels which result in lower drive and higher cell-to-cell performance variations.
Innovation Solution
The development of a 3D semiconductor device with a single crystal layer and metal gate transistors, utilizing a multilayer structure with alternating porosity levels to form monocrystalline channels, reducing construction costs and improving performance by sharing lithography steps, and incorporating a digital-to-analog converter and cache memory circuits for enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If 3D stacking of semiconductor devices is implemented, then wire lengths are reduced and wiring delay is kept low, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements 3D stacking of memory layers vertically above the logic layer, transitioning from 2D planar integration to 3D vertical integration. This dimensional change reduces wire lengths by placing memory cells closer to the logic circuits that access them, thereby reducing wiring delay while managing the complexity through systematic layer stacking approaches
2Ease of manufacture
If poly-silicon channels are used in 3D memory, then manufacturing is simpler, but drive current is lower and cell-to-cell performance variation is higher
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. This parameter change improves carrier mobility and drive current while reducing cell-to-cell performance variation. The monocrystalline structure provides more uniform electrical properties across different memory cells, enhancing reliability while maintaining manufacturability through established semiconductor processing techniques
3Quantity of substance
If memory capacity is increased through scaling, then more bits per cell are achieved, but wire degradation occurs leading to high energy cost and latency
Solution Approach 1:
The patent employs 3D vertical stacking to increase memory capacity by stacking multiple memory layers above the logic layer, rather than continuing to scale lateral dimensions. This vertical expansion increases bits per cell while keeping interconnect lengths short, as memory cells are positioned directly above their accessing logic circuits. The short vertical distances minimize wire degradation and reduce the energy cost for memory fetch operations
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one digital to analog converter circuit, and where the device includes a hybrid bonding layer.