3D Memory Hybrid Bonding Contacts With Through-Array Interconnects
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and increasing costs, necessitating the development of three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
The implementation of through array contact (TAC) structures in 3D NAND memory devices, which include an alternating layer stack with dielectric and conductor pairs, barrier structures, and through array contacts to facilitate vertical interconnects between memory arrays and peripheral circuits, reducing process complexity and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar memory cell scaling is continued to increase memory density, then memory density improves, but feature size approaches lower limit making process and fabrication challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory structure stacks memory cells vertically across multiple layers, enabling continued memory density improvement without further reducing lateral feature sizes. This dimensional change allows fabrication processes to operate at existing feature size limits while achieving higher density through vertical stacking.
2Productivity
If three-dimensional memory architecture is implemented to increase memory density, then memory density improves, but device complexity increases
Solution Approach 1:
The 3D memory device is segmented into distinct functional regions: alternating dielectric stack regions, alternating conductor/dielectric stack regions, and through-array contact regions. Barrier structures further divide the alternating conductor/dielectric stack into separate memory fingers. This segmentation allows each region to be optimized independently and simplifies the fabrication process by breaking down the complex 3D structure into manageable segments.
Solution Approach 2:
Through-array contacts serve as intermediary structures that extend vertically through the alternating dielectric stack to provide electrical connections between upper and lower interconnection layers. These intermediary contacts simplify the overall device complexity by providing direct vertical interconnect paths, eliminating the need for complex lateral routing through multiple interconnection layers.
3Reliability
If traditional interconnection structures are used in 3D memory, then electrical connectivity is achieved, but metal levels increase leading to larger die size
Solution Approach 1:
Through-array contacts act as intermediary vertical interconnect structures that penetrate the alternating dielectric stack directly, providing electrical pathways between upper and lower interconnection layers without requiring additional metal levels. This intermediary approach reduces the total number of metal levels needed, thereby reducing die size while maintaining electrical connectivity.
Solution Approach 2:
The interconnection architecture transitions from lateral routing through multiple metal levels to vertical routing through the alternating dielectric stack. By utilizing the vertical dimension for interconnection, the patent reduces the number of metal levels required and decreases overall die size while maintaining reliable electrical connectivity between memory arrays and peripheral circuits.
Data Source
AI summary
A method for forming a memory device is provided. An alternating dielectric stack is formed on a substrate. The alternating dielectric stack includes a dielectric layer pair, and the dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. A barrier structure extending vertically through the alternating dielectric stack and laterally separating the alternating dielectric stack into a first portion and a second portion is formed. The barrier structure has an unclosed shape. The first dielectric layer in the second portion of the alternating dielectric stack is replaced with a conductor layer to form an alternating conductor/dielectric stack including the conductor layer and a third dielectric layer. A through array contact structure extending vertically through the first portion of the alternating dielectric stack to the substrate is formed. A slit extending vertically through the second portion of the alternating dielectric stack is formed. A conductive material is deposited into the slit to form a slit structure.