3D Memory Stack with Hybrid Bonding for High-Density Interconnects
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Solution Overview
Problem
As feature sizes of planar semiconductor devices approach their limits, conventional fabrication techniques become challenging and costly, necessitating a more efficient method for forming high-density memory devices.
Innovation Solution
A 3D memory device architecture is developed by stacking semiconductor substrates and forming interconnections vertically, utilizing bonding techniques such as hybrid bonding to create a high-density interconnect structure, with a memory array and peripheral devices formed on separate substrates and bonded together, and an interconnection layer formed over the peripheral device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor devices are scaled to smaller sizes by improving process technology, then device density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) semiconductor device architecture to three-dimensional (3D) stacked architecture. Multiple semiconductor substrates are bonded vertically to form a stack, enabling continued density improvement by utilizing the vertical dimension rather than further scaling lateral dimensions, thereby avoiding the fabrication complexity and cost associated with extreme planar scaling
Solution Approach 2:
The device is divided into multiple independent semiconductor substrates (first substrate, second substrate, etc.) that are fabricated separately and then bonded together. Each substrate can be optimized independently, and the segmentation allows parallel fabrication processes, reducing overall fabrication complexity while achieving high device density through vertical stacking
2Quantity of substance
If feature sizes of planar semiconductor devices approach lower limit, then device density is improved, but manufacturing cost and difficulty increase
Solution Approach 1:
By moving to 3D stacked architecture, the patent achieves higher device density without further reducing lateral feature sizes to their lower limits. The vertical stacking approach allows manufacturing at more feasible feature sizes while still achieving high density through increased vertical integration
Solution Approach 2:
Multiple semiconductor substrates are fabricated separately in advance using conventional manufacturing processes at optimal feature sizes, then bonded together in a preliminary assembly step. This preliminary fabrication of individual substrates avoids the need to push planar feature sizes to their lower limits, maintaining manufacturing ease while achieving high density
3Quantity of substance
If semiconductor substrates are stacked vertically to form 3D structure, then device density is improved, but interconnection complexity increases
Solution Approach 1:
Bonding interfaces and interconnection structures are introduced as intermediaries between the vertically stacked semiconductor substrates. These intermediaries provide standardized connection points that simplify the interconnection process, enabling vertical integration while managing interconnection complexity through structured bonding approaches
Solution Approach 2:
The interconnection system is segmented into discrete bonding interfaces between individual substrate pairs. Each interface can be designed and fabricated independently using standardized processes, reducing overall interconnection complexity compared to a monolithic interconnection structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables performance improvements at reduced power consumption and smaller footprint, addressing the density limitations of planar semiconductor devices while maintaining efficient operation and reliability.
Implementation Method 1
A second substrate is bonded to the first dielectric layer
Implementation Method 2
A heterogeneous interface is formed in the second substrate
Implementation Method 3
An interconnection layer is formed over the peripheral device
Data Source
AI summary
A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.