3D Memory Hybrid Staircase Structure for Dense Vertical Stacking
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating hybrid staircase structures that allow for optimal spacing and connectivity of memory elements, leading to reduced storage density and performance.
Innovation Solution
A three-dimensional memory device is designed with alternating stacks of insulating and conductive layers forming a hybrid staircase structure, where the lateral extent of conductive layers decreases with vertical distance from the substrate, and trench fill structures connect these stacks, enabling vertical memory stacks and retro-stepped dielectric material portions for enhanced interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If alternating stacks of insulating and conductive layers are formed with lateral extent of conductive layers decreasing with vertical distance, then storage density is increased, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into multiple alternating stacks of insulating and conductive layers, with each stack containing memory elements at different vertical levels. The conductive layers are segmented to create the staircase configuration, where the lateral extent decreases with vertical distance, allowing independent formation and processing of each layer segment.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional staircase structure by adding vertical dimensionality. The conductive layers are extended vertically with decreasing lateral extent, creating multiple storage levels within the same footprint area, thereby increasing storage density through spatial utilization in three dimensions.
2Adaptability or versatility
If trench fill structures are used to connect neighboring alternating stacks, then interconnectivity is improved, but device complexity increases
Solution Approach 1:
Trench fill structures are introduced as intermediary elements that connect neighboring alternating stacks. These trench fill structures fill the spaces between adjacent stacks and provide conductive or insulating pathways that enable electrical connection between memory elements on different stacks, facilitating three-dimensional interconnectivity.
Solution Approach 2:
The trench fill structures are nested within the three-dimensional array of alternating stacks, fitting into the spaces between adjacent stacks. This nesting approach allows the interconnect structures to be integrated within the existing memory architecture without requiring separate interconnection layers, thereby improving connectivity while managing complexity.
3Manufacturing precision
If retro-stepped dielectric material portions are formed with continuous boundaries extending to different heights, then manufacturing precision is increased, but storage density is reduced
Solution Approach 1:
The dielectric material portions are formed with different local properties at different horizontal positions. The retro-stepped configuration creates regions where the dielectric material extends to different heights, with continuous boundaries on one side and stepped boundaries on the other, allowing precise control of electrical fields and isolation characteristics in different locations within the same structure.
Data Source
AI summary
A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.