3D Memory Gate Structure With Hybrid STI Source Contacts
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Solution Overview
Problem
Conventional methods for forming 3D memory devices face challenges such as difficult channel hole etch profiles, unstable electrical connections, and slower erase operations due to the use of silicon selective epitaxial growth (SEG) and punching etching, which induce damage and limit the efficiency of carrier control between the source and drain.
Innovation Solution
The method forms hybrid shallow trench isolation structures with both dielectric and conductive materials, reducing contact resistance and improving carrier control by replacing heavily doped crystalline silicon regions with a hybrid structure, and forming array common source contacts in a way that enhances electrical connections and reduces damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon selective epitaxial growth (SEG) and punching etching are used to form 3D memory devices, then the manufacturing process can be completed, but the channel hole etch profile becomes difficult and damage is induced limiting carrier control efficiency
Solution Approach 1:
The patent changes the material parameter of the source region from crystalline silicon to amorphous silicon, which fundamentally alters the etching behavior and eliminates the difficult etch profile problem associated with SEG processes. This parameter change in material structure enables better carrier control while simplifying the manufacturing process.
Solution Approach 2:
The patent uses amorphous silicon as a sacrificial material that can be easily removed through standard etching processes. This disposable approach to source region formation eliminates the need for complex SEG processes and punching etching, thereby improving channel hole etch profiles without compromising manufacturing completion.
2Ease of manufacture
If heavily doped crystalline silicon regions are used in 3D memory devices, then the source and drain regions can be formed, but contact resistance increases and carrier control becomes unstable
Solution Approach 1:
The patent employs a composite structure combining amorphous silicon source/drain regions with selectively epitaxially grown channel regions. This composite approach allows the amorphous silicon to provide low contact resistance while the crystalline channel maintains high carrier mobility, thereby improving both electrical connection stability and carrier control.
Solution Approach 2:
The patent applies different material qualities to different regions: amorphous silicon is used in the source/drain regions where low contact resistance is critical, while crystalline silicon is used in the channel regions where high carrier mobility is essential. This local differentiation of material quality optimizes both contact stability and carrier control.
3Productivity
If conventional 3D memory device structures are used, then the basic memory function can be achieved, but erase operations are slow due to damaged carrier control
Solution Approach 1:
The patent changes the carrier control mechanism by using amorphous silicon source/drain regions that enable more efficient carrier injection and extraction. This parameter change in material structure directly improves erase operation speed by enhancing carrier control efficiency without compromising reliability.
Data Source
AI summary
A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.