3D Memory Device III-V Compound Semiconductor Channel Contacts
Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high-density storage with efficient III-V compound semiconductor channel and source/drain contacts, particularly in forming reliable memory opening fill structures with graded III-V compound semiconductor materials for optimal conductivity and storage capabilities.
Innovation Solution
A three-dimensional memory device is developed with a III-V compound semiconductor channel and source/drain contacts, featuring a substrate with an alternating stack of insulating and electrically conductive layers, where memory openings are filled with a III-V compound semiconductor pedestal, channel, and graded drain region, enabling efficient conductivity and storage. The method involves forming a III-V compound substrate semiconductor layer, creating an alternating stack, and forming memory openings filled with a III-V compound semiconductor pedestal and channel, along with a graded drain region for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory devices are used, then manufacturing process is simpler, but storage density and conductivity are insufficient
Solution Approach 1:
The patent employs composite material structures by integrating III-V compound semiconductor layers with silicon substrate, creating heterostructures with graded composition (e.g., InGaAs layers with varying indium content). This composite approach enables higher storage density and improved conductivity while managing lattice mismatch through compositional grading, directly resolving the contradiction between enhanced performance and structural complexity
Solution Approach 2:
The invention applies local quality by implementing graded buffer layers with progressively changing composition (e.g., GaSb to InGaAs transitions with varying indium content) at specific interfaces. This localized compositional variation optimizes lattice matching and reduces dislocation density at critical interfaces, enabling high-density storage without compromising overall device reliability
2Reliability
If III-V compound semiconductor materials are integrated, then conductivity and storage capability improve, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes by systematically varying the composition of III-V compound semiconductor layers (e.g., changing indium content in InGaAs from 0% to 30% across different layers) to optimize conductivity and lattice matching. This controlled parameter variation enables reliable electrical performance while maintaining compatibility with existing semiconductor manufacturing processes
Solution Approach 2:
The invention introduces graded buffer layers as intermediary structures between silicon substrate and III-V compound semiconductor channels. These buffer layers with progressive composition changes (e.g., GaSb→InGaAs transitions) act as mediators that reduce lattice mismatch and dislocation density, enabling reliable conductivity without requiring complete overhaul of manufacturing processes
3Productivity
If graded III-V compound semiconductor material is used, then conductivity and storage performance are optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the graded buffer structure into multiple discrete layers with stepwise composition changes rather than continuous gradients. This segmentation approach (e.g., separate InGaAs layers with progressively increasing indium content) maintains the beneficial effects of graded matching while relaxing manufacturing precision requirements, enabling efficient production with standard epitaxial equipment
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.