3D Memory Stack With III-V Vertical Channels for Higher Density
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high-density storage and efficient semiconductor channel formation, particularly in integrating III-V compound semiconductor channels within complex memory stack structures.
Innovation Solution
The method involves forming a three-dimensional memory device by providing a substrate with a silicon oxide layer and a single-crystalline germanium-containing layer, growing a single-crystalline III-V compound semiconductor layer, and creating an alternating stack of insulating and spacer material layers, which are later replaced with electrically conductive layers, to form memory openings and fill structures with vertical semiconductor channels connected to the III-V compound semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory devices are used, then manufacturing process is simpler, but storage density and performance are limited
Solution Approach 1:
The patent employs composite material structures by integrating III-V compound semiconductor layers with silicon-germanium buffer layers and alternating stacks of insulating and conductive materials. This composite approach enables high-density storage by leveraging the superior electrical properties of III-V compounds while maintaining manufacturability through systematic layer integration
Solution Approach 2:
The invention transitions from planar memory structures to three-dimensional vertical stacks with alternating insulating and conductive layers arranged in multiple dimensions. Memory openings extend vertically through the alternating stack, creating a multi-dimensional architecture that dramatically increases storage density while organizing complexity in a structured manner
2Productivity
If III-V compound semiconductor channels are integrated, then channel efficiency and performance improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by first forming a silicon-germanium buffer layer with graded composition before depositing the III-V compound semiconductor layer. This preparatory step creates an optimized substrate that facilitates subsequent epitaxial growth, ensuring high-quality channel formation while simplifying the overall manufacturing process
Solution Approach 2:
The silicon-germanium buffer layer serves as an intermediary between the silicon substrate and the III-V compound semiconductor channel. This intermediate layer mediates the interface properties, enabling efficient integration of the high-performance III-V material while maintaining manufacturing feasibility through standardized deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory devices with efficient semiconductor channels, enhancing storage capacity and performance by leveraging the properties of III-V compound semiconductor materials.
Implementation Method 1
growing a single-crystalline III-V compound semiconductor layer on the single-crystalline germanium-containing layer
Data Source
AI summary
A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.