3D Semiconductor Memory Source Structure for Impurity Diffusion Control
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive equipment needed for fine pattern formation, making it impractical to increase memory cell density, while three-dimensional semiconductor devices offer a potential solution but require improved reliability.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a first source conductive pattern of polycrystalline material with smaller crystal grains, a stack of gate electrodes, and a vertical channel portion that penetrates the stack and is in contact with the source conductive pattern, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the grain size of the source conductive pattern is reduced to improve reliability, then the amount of grain boundaries increases which can trap impurities, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the grain size of the source conductive pattern within a specific range (0.5-5 micrometers) to optimize the balance between reliability improvement through grain boundary impurity trapping and manufacturing feasibility. This parameter optimization resolves the contradiction by finding the optimal grain size range that provides sufficient grain boundaries for impurity trapping while remaining manufacturable with existing processes.
Solution Approach 2:
The patent employs composite materials by creating a polycrystalline source conductive pattern with controlled grain structures and specific impurity distributions. The composite nature arises from the combination of multiple crystal grains with different orientations and the strategic distribution of impurities at grain boundaries, which together enhance reliability while managing manufacturing complexity through material design rather than process complexity.
2Reliability
If impurities are increased in the source conductive pattern to improve electrical characteristics, then the electrical performance improves, but the risk of impurity diffusion into the vertical channel portion increases
Solution Approach 1:
The patent uses grain boundaries as intermediary structures that act as traps for impurities, preventing them from diffusing into the vertical channel portion. The grain boundaries serve as a mediating layer that holds impurities in the source conductive pattern while blocking their migration path to the channel, thus resolving the contradiction between needing impurities for electrical performance and preventing their harmful diffusion.
Solution Approach 2:
The patent applies local quality by creating non-uniform impurity distribution within the source conductive pattern, concentrating impurities at grain boundaries rather than uniformly distributing them. This localized impurity placement at specific regions (grain boundaries) provides the electrical benefits where needed while preventing harmful diffusion to the channel, resolving the contradiction through spatially differentiated impurity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and integration density of three-dimensional semiconductor memory devices by reducing grain size in the source conductive pattern, increasing the amount of impurities, and preventing impurity diffusion into the vertical channel portion, thereby enhancing electric and reliability characteristics.
Implementation Method 1
a first source conductive pattern comprising a polycrystalline material including first crystal grains, the first source conductive pattern on a substrate, the substrate comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains
Implementation Method 2
increasing the amount of impurities, and preventing impurity diffusion into the vertical channel portion
Data Source
AI summary
A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.