3D Memory Interconnect Layout for Lower Bit-Line Capacitance
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Solution Overview
Problem
The reduction in pitch between interconnects in three-dimensional memory devices leads to increased parasitic capacitance, deteriorating the write and read performance of memory cells.
Innovation Solution
The semiconductor device incorporates a unique structure with bit lines and source lines disposed both below and above a memory cell array, increasing the pitch between interconnects and reducing parasitic capacitance, thereby enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between interconnects is reduced to increase integration density, then the number of memory cells per unit area increases, but the parasitic capacitance of bit lines increases causing performance deterioration
Solution Approach 1:
The patent transitions from a planar interconnect arrangement to a three-dimensional configuration by placing bit lines on both sides of the memory cell array. This dimensional change allows bit lines to extend in opposite directions from the memory array, effectively doubling the available interconnect routing space and increasing pitch without sacrificing integration density.
Solution Approach 2:
The bit line interconnect system is segmented into multiple independent bit lines extending from opposite sides of the memory cell array. This segmentation allows each bit line to have sufficient pitch and reduces the parasitic capacitance burden on any single bit line, while collectively maintaining high integration density through the multi-sided arrangement.
2Quantity of substance
If the pitch between bit lines is reduced to increase memory capacity, then more bit lines can be packed, but the write and read performance of memory cells deteriorates
Solution Approach 1:
The patent employs a three-dimensional interconnect architecture where bit lines extend from multiple sides (at least two opposite sides) of the memory cell array. This spatial arrangement increases the effective pitch between bit lines by utilizing vertical and lateral dimensions, thereby reducing parasitic capacitance and improving signal integrity for both read and write operations while maintaining high memory capacity.
Solution Approach 2:
The bit line network is divided into multiple segments extending from different sides of the memory array. Each segment serves a specific region of memory cells, reducing the total capacitance load on any individual bit line segment. This segmentation enables higher memory capacity through increased bit line count while preserving performance through reduced parasitic effects on each segment.
Data Source
AI summary
In one embodiment, a semiconductor device includes a memory cell array, a first interconnect layer provided below the memory cell array, and including a plurality of first bit lines that extend in a first direction, and a second interconnect layer provided below the memory cell array, and including a plurality of first source lines that extend in a second direction different from the first direction, the second interconnect layer being different from the first interconnect layer. The device further includes a third interconnect layer provided above the memory cell array, and including a plurality of second source lines that extend in the second direction, and a fourth interconnect layer provided above the memory cell array, and including a plurality of second bit lines that extend in the first direction, the fourth interconnect layer being different from the third interconnect layer.