3D Memory Interconnect Transfer Using Single-Crystal Silicon
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Solution Overview
Problem
The existing technologies for 3D memory devices face challenges in increasing memory density and performance due to limitations in polysilicon inter-deck plugs and source layers, which result in reduced carrier mobility and increased fabrication complexity.
Innovation Solution
The use of single-crystal silicon layers, transferred via a de-bonding process, as inter-deck plugs or source layers, which offers higher carrier mobility and improved electrical performance, along with a silicon-dielectric bonding process that enhances yield and bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon inter-deck plugs and source layers are used in 3D memory devices, then fabrication can be performed using conventional processes, but carrier mobility is reduced and fabrication complexity increases
Solution Approach 1:
The patent changes the material parameter from polysilicon to single-crystal silicon, fundamentally altering the crystal structure to achieve higher carrier mobility while maintaining compatibility with conventional fabrication processes through transferred interconnect layer technology
Solution Approach 2:
The patent introduces a transferred interconnect layer as an intermediary structure that enables single-crystal silicon to be integrated into the 3D memory device. This transferred layer acts as a mediator that bridges the single-crystal silicon source layer with the memory stack, allowing high-performance material integration without requiring complete process overhaul
2Ease of manufacture
If polysilicon inter-deck plugs and source layers are used in 3D memory devices, then conventional fabrication processes can be maintained, but fabrication complexity and cycle time increase
Solution Approach 1:
The patent performs preliminary actions by forming the single-crystal silicon layer and interconnect structures on a separate substrate before transfer. This preliminary fabrication allows complex single-crystal silicon structures to be created using conventional processes, then transferred as a complete unit to reduce overall fabrication complexity
Solution Approach 2:
The patent segments the fabrication process into distinct stages: forming single-crystal silicon structures on a donor substrate, preparing the memory stack, transferring the interconnect layer with single-crystal silicon, and integrating with the memory device. This segmentation allows each stage to be optimized independently while maintaining conventional process compatibility
3Reliability
If single-crystal silicon layers are transferred via de-bonding process, then carrier mobility and electrical performance are improved, but fabrication process complexity increases
Solution Approach 1:
The patent uses a transferred interconnect layer as an intermediary vehicle that carries the single-crystal silicon layer from the donor substrate to the memory stack. This intermediary approach allows the de-bonding and transfer process to be performed on a manageable layer structure, reducing the complexity impact compared to direct single-crystal silicon integration
Solution Approach 2:
The patent merges the single-crystal silicon source layer formation with the interconnect layer transfer process. By combining these functions into a single transferred structure, the patent reduces the number of separate fabrication steps required, thereby mitigating the increase in fabrication process complexity while achieving improved electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher cell storage capacity and better performance at inter-deck joints and source layers, while also reducing fabrication complexity and cycle time, and improving device yield.
Implementation Method 1
The single-crystal silicon layer and the interconnect layer formed thereon are transferred from the second substrate onto the memory stack above the first substrate
Implementation Method 2
along with a silicon-dielectric bonding process that enhances yield and bonding strength
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. A memory stack including interleaved sacrificial layers and dielectric layers is formed above a first substrate. A channel structure extending vertically through the memory stack is formed. A single-crystal silicon layer is formed in a second substrate. An interconnect layer including a bit line is formed on the single-crystal silicon layer above the second substrate. The single-crystal silicon layer and the interconnect layer formed thereon are transferred from the second substrate onto the memory stack above the first substrate, such that the bit line in the interconnect layer is electrically connected to the channel structure.