3D Semiconductor Memory Stack With Interlayer Capacitors
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive equipment required for fine pattern formation, which restricts their ability to increase storage capacity and reduce size effectively.
Innovation Solution
A three-dimensional semiconductor memory device is developed, featuring a stack structure with interlayers and gate electrodes, a stepwise pad structure, and interlayer capacitors, which allows for a more compact design and increased storage capacity by utilizing a peripheral circuit structure and cell array structure bonded through bonding pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are highly integrated to increase storage capacity, then storage capacity is improved, but the manufacturing cost increases due to expensive processing equipment required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. By stacking multiple memory layers vertically, the device achieves higher storage capacity without requiring finer lateral patterning, thus avoiding the need for expensive fine-pattern processing equipment while increasing integration density.
Solution Approach 2:
The patent divides the memory device into multiple stacked layers, with peripheral circuit structures and cell array structures formed separately and then bonded together. This segmentation allows independent optimization of each structure and enables the use of different fabrication processes for each layer, reducing overall manufacturing complexity and cost.
2Volume of moving object
If two-dimensional or planar semiconductor devices are highly integrated to reduce device size, then device size is reduced, but the manufacturing cost increases due to expensive processing equipment required for fine pattern formation
Solution Approach 1:
The patent employs vertical stacking of multiple memory layers to reduce the lateral footprint of the device. By utilizing the vertical dimension for expansion, the device achieves compact size without requiring extremely fine lateral patterning, thereby avoiding expensive fine-pattern processing equipment while maintaining small device footprint.
Solution Approach 2:
The patent separates peripheral circuit structures and cell array structures into distinct layers that are fabricated independently and then bonded together. This segmentation enables optimized fabrication processes for each component and reduces the complexity of forming fine patterns in a single monolithic structure, lowering manufacturing costs while achieving compact device size.
3Productivity
If peripheral circuit structure and cell array structure are bonded through bonding pads using a separate bonding process, then manufacturing efficiency is improved and costs are reduced, but device complexity increases due to additional bonding steps
Solution Approach 1:
The patent divides the memory device into separately fabricable peripheral circuit structures and cell array structures that are bonded together through bonding pads. This segmentation allows each structure to be manufactured using optimized, independent processes, improving overall manufacturing efficiency and reducing costs despite the additional bonding step.
Solution Approach 2:
The patent introduces bonding pads as intermediary structures that facilitate the connection between peripheral circuit structures and cell array structures. These bonding pads serve as standardized interfaces that simplify the bonding process and enable modular assembly, reducing process complexity while maintaining manufacturing efficiency.
Data Source
AI summary
Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayers and gate electrodes and including a pad part having a stepwise structure on the contact region, a first dielectric layer covering the pad part of the stack structure, a second dielectric layer on the first dielectric layer, an interlayer capacitor between the first dielectric layer and the second dielectric layer, cell contact plugs penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and correspondingly connected to the gate electrodes, and lower and upper conductive lines penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and electrically connected to the interlayer capacitor.