3D Non-Volatile Memory With Interleaved Vertical Select Devices
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Solution Overview
Problem
Existing non-volatile memory arrays face challenges in reducing leakage currents and complexity, particularly when operating multiple memory elements in parallel, which can lead to inaccurate data reading and increased power consumption.
Innovation Solution
A three-dimensional array architecture with vertically oriented bit lines and select devices that connect local bit lines to global bit lines, eliminating the need for diodes and simplifying the manufacturing process, allowing for a larger number of addressed memory elements without errors and within reasonable power supply capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If diodes are connected in series with variable resistive elements to reduce leakage currents, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent removes diodes from the memory cell structure entirely, extracting the harmful element that added complexity. Instead of using diodes to control current flow, the invention relies on the inherent properties of the variable resistive elements and the applied voltage patterns to achieve selective addressing without requiring additional current-blocking components.
Solution Approach 2:
The variable resistive elements serve their dual function of data storage and current control without requiring external diodes. The memory cells self-regulate current flow through their resistance states and the applied voltage patterns, eliminating the need for separate diode components to prevent leakage.
2Productivity
If reading or programming voltages are applied to a large number of memory elements in parallel, then productivity increases, but harmful factors increase due to leakage currents through unselected memory elements
Solution Approach 1:
The patent applies voltages to more memory elements than strictly necessary for the selected address, relying on the fact that only the specifically addressed cell will have the precise voltage combination that triggers state change or readable signal. This partial action approach enables parallel operation while avoiding the need to perfectly isolate each selected cell.
3Ease of manufacture
If a two-dimensional array architecture is used with diodes, then manufacturing is simplified, but the number of addressed memory elements is limited due to leakage and power consumption
Solution Approach 1:
The patent transitions from a two-dimensional array to a three-dimensional cross-point architecture where bit lines and word lines intersect in three-dimensional space. This dimensional change allows significantly more memory elements to be addressed simultaneously while maintaining manufacturing simplicity through the same basic fabrication processes applied to layered structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture reduces leakage currents, simplifies manufacturing, and enables a higher density of memory storage elements while maintaining accurate data reading and efficient power usage, allowing for a larger number of memory elements to be operated in parallel without errors.
Implementation Method 1
non-volatile memory uses variable resistance memory elements that may be set to either low or high resistance states
Data Source
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AI summary
A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.