3D Ferroelectric Memory Layout for Fast Switching Without Gate Damage
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Solution Overview
Problem
Current 3D NAND flash memory devices face challenges in reducing operating voltage and increasing programming speed while preventing deterioration of the gate insulating layer due to high electric fields applied during ferroelectric polarization switching.
Innovation Solution
The 3D ferroelectric memory device design includes a structure with a ferroelectric layer, intermediate electrode, and gate insulating layer, where the intermediate electrode protrudes from the insulating layers, increasing the area of the gate insulating layer in contact with the channel layer, thereby enhancing the capacitance ratio and reducing the electric field intensity, allowing for lower operating voltage and faster programming speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high electric field is applied to switch ferroelectric polarization, then programming speed is improved, but gate insulating layer deteriorates
Solution Approach 1:
The patent introduces an intermediate electrode as a mediator between the gate electrode and the ferroelectric layer. This intermediate electrode allows the application of high electric fields for fast programming while protecting the gate insulating layer from direct exposure to these high fields, thus preventing deterioration and maintaining reliability.
Solution Approach 2:
The gate structure is segmented into multiple components: a gate electrode, an intermediate electrode, and a gate insulating layer. This segmentation allows the high electric field to be applied locally at the intermediate electrode-ferroelectric layer interface for fast programming, while the gate insulating layer is protected from direct high field exposure, resolving the contradiction between speed and reliability.
2Use of energy by moving object
If operating voltage is reduced, then energy consumption is improved, but ferroelectric polarization switching becomes difficult
Solution Approach 1:
The intermediate electrode serves as a mediator that enables effective polarization switching at lower operating voltages. By concentrating the electric field at the intermediate electrode-ferroelectric layer interface, the structure achieves efficient polarization switching with reduced voltage, thereby lowering energy consumption while maintaining switching effectiveness.
Solution Approach 2:
The patent creates a local high electric field region at the intermediate electrode-ferroelectric layer interface, while the overall gate voltage can be kept low. This local quality enhancement allows effective polarization switching to occur at specific locations even when the average operating voltage is reduced, resolving the contradiction between energy efficiency and switching effectiveness.
3Reliability
If intermediate electrode protrudes from insulating layers, then gate insulating layer area increases and electric field intensity decreases, but device complexity increases
Solution Approach 1:
The intermediate electrode protrudes in the vertical dimension from the insulating layers, creating an extended structure that increases the effective area of the gate insulating layer without requiring lateral expansion. This dimensional change provides additional protection and field distribution benefits while maintaining a relatively compact planar footprint, balancing reliability improvement with acceptable complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the operating voltage, increases programming speed, and improves the reliability of the 3D ferroelectric memory device by limiting gate insulating layer deterioration and enhancing on-current through increased channel layer width.
Implementation Method 1
a plurality of ferroelectric layers in contact with the plurality of gate electrodes
Implementation Method 2
increasing the area of the gate insulating layer in contact with the channel layer, thereby enhancing the capacitance ratio and reducing the electric field intensity
Implementation Method 3
enhancing the capacitance ratio
Data Source
AI summary
A three-dimensional (3D) ferroelectric memory device may include a substrate; a plurality of insulating layers stacked on the substrate; a plurality of gate electrodes between the plurality of insulating layers; a plurality of ferroelectric layers in contact with the plurality of gate electrodes; a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers and protruding from side surfaces of the plurality of insulating layers; a gate insulating layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers; and a channel layer in contact with the gate insulating layer.