3D Ferroelectric Memory Structure With Intermediate Electrodes
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Solution Overview
Problem
Existing 3D NAND flash memory devices face challenges in achieving high integration and efficient data storage with low operating voltage and high programming rates, as well as limitations in memory window and on-current due to the absence of intermediate electrodes in ferroelectric field-effect transistors (FeFETs).
Innovation Solution
The introduction of intermediate electrodes in a 3D ferroelectric memory device with a metal-insulator-metal-ferroelectric-semiconductor (MIMFS) structure, where each electrode is configured with a specific polarity, and the channel layer is designed in a three-dimensional shape to increase the memory window and on-current by applying charges to the intermediate electrodes, which are floating electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 3D NAND flash memory structure is used, then device integration is achieved, but programming rate is insufficient and operating voltage is high
Solution Approach 1:
The gate structure is segmented into multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) stacked vertically, with intermediate electrodes positioned between them. This segmentation allows independent control of different gate regions, enabling optimized programming sequences that improve programming rate while reducing required operating voltage through distributed voltage application.
Solution Approach 2:
The patent transitions from planar gate control to three-dimensional vertical gate stacking, adding the vertical dimension to gate electrode arrangement. The intermediate electrodes extend protrusively from side surfaces of insulating layers, creating a multi-layered vertical architecture that increases channel width and enhances programming efficiency without increasing planar footprint.
2Productivity
If FeFET is integrated into 3D NAND structure, then low operating voltage and high programming rate are achieved, but device complexity increases
Solution Approach 1:
Multiple functional components are merged into a unified vertical stack: gate electrodes, intermediate electrodes, insulating layers, ferroelectric layers, and channel layers are integrated into a single compact structure. This merging reduces the overall device footprint and simplifies manufacturing processes while maintaining the low-voltage, high-speed FeFET functionality.
Solution Approach 2:
The intermediate electrodes serve multiple functions: they act as charge storage elements, extend channel width to increase on-current, and provide structural support for the vertical gate stacking. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity.
3Reliability
If intermediate electrodes extend protrusively to increase channel width, then on-current increases, but manufacturing precision requirements increase
Solution Approach 1:
The intermediate electrodes are formed with predetermined protruding lengths during the fabrication process, extending beyond the side surfaces of insulating layers by specific distances (e.g., 10-50 nm). This preliminary positioning ensures optimal channel width enhancement while establishing clear manufacturing targets that guide subsequent processing steps, reducing the actual precision burden during assembly.
Solution Approach 2:
The intermediate electrodes act as intermediary structures between the gate electrodes and the channel layer, providing a controlled transition zone that enhances channel width without requiring direct high-precision alignment between all components. The protruding portions serve as buffer zones that tolerate minor positioning variations while maintaining effective channel enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the memory window and on-current of FeFETs by increasing the coercive voltage and channel width, thereby improving data storage efficiency and performance in 3D NAND flash memory devices.
Implementation Method 1
a ferroelectric layer in contact with side surfaces of the plurality of insulating layers
Implementation Method 2
Each of the plurality of intermediate electrodes may be configured to include a charge of a first polarity
Data Source
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AI summary
Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate (105), a plurality of insulating layers (111) stacked on the substrate, a plurality of gate electrodes (170) between the plurality of insulating layers, a plurality of gate insulating layers (160) in contact with the plurality of gate electrodes, a plurality of intermediate electrodes (120) in contact with the plurality of gate insulating layers, a ferroelectric layer (130) in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer (140) in contact with the ferroelectric layer.