3D Memory Architecture With Inter-Tier Vias for Routing Efficiency
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Solution Overview
Problem
Conventional two-dimensional integrated circuits face challenges in miniaturization and power consumption due to complex routing requirements, especially in memory elements, which limits the integration of more powerful and efficient memory within the limited space of mobile communication devices.
Innovation Solution
The development of multi-dimensional integrated circuit architecture that utilizes all planes of an electronic board for semiconductor circuitry, employing monolithic multi-dimensional memory structures with crossbar architecture, tight-pitched vertical, horizontal, and angled monolithic intertier vias for efficient inter-unit routing, and control logic to configure memory banks, enabling terabyte memory capacity on the same space as gigabytes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional integrated circuit designs are used, then manufacturing and routing are simpler, but memory capacity and integration density are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional integrated circuit layouts to three-dimensional stacked architectures. Multiple memory layers are stacked vertically with through-silicon vias (TSVs) providing inter-layer connections. This dimensional change enables significantly increased memory capacity within the same footprint area while distributing routing complexity across multiple layers rather than concentrating it in a single plane.
2Quantity of substance
If memory capacity is increased within limited space, then more powerful memory integration is achieved, but power consumption and heat generation increase
Solution Approach 1:
The patent divides the memory system into multiple independent stacked layers, each functioning as a separate memory module. This segmentation allows for selective activation of specific layers based on memory capacity requirements, enabling the system to consume power only for the layers that are actively being used, thereby reducing overall power consumption while maintaining high total memory capacity.
3Productivity
If active elements are increased to provide increased functionality, then performance is improved, but routing requirements become increasingly complex
Solution Approach 1:
The patent resolves routing complexity by utilizing the third dimension (vertical stacking) to separate different signal paths and interconnections. Through-silicon vias provide direct vertical connections between layers, eliminating the need for complex lateral routing that would be required in a two-dimensional layout. This allows for increased numbers of active elements and enhanced functionality without proportionally increasing routing complexity.
Data Source
AI summary
Monolithic multi-dimensional integrated circuits and memory architecture are provided. Exemplary integrated circuits comprise an electronic board having a first side and a second side, a multi-dimensional electronic package having multiple planes, and one or more semiconductor wafers mounted on the first side and the second side of the electronic board and on the multiple planes of the electronic package. Exemplary monolithic multi-dimensional memory architecture comprises one or more tiers, one or more monolithic inter-tier vias spanning the one or more tiers, at least one multiplexer disposed in one of the tiers, and control logic determining whether memory cells are active and which memory cells are active and controlling usage of the memory cells based on such determination. Each tier has a memory cell, and the inter-tier vias act as crossbars in multiple directions. The multiplexer is communicatively coupled to the memory cell in the respective tier. In exemplary embodiments, the one or more semiconductor wafers include one or more solar cells. The solar cells may comprise MEMS and/or on-chip solar cells.