3D Memory Cell Structure With Isolated Channels for Signal Isolation
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing memory cell integration and reliability due to signal interference between adjacent cells, requiring improved structural stability and efficient data storage techniques.
Innovation Solution
A three-dimensional non-volatile memory device is designed with a gate structure featuring alternately stacked gate electrode layers and interlayer insulating layers, a data storage layer, and a channel layer, where each layer is discontinuous in the vertical direction, isolated by interlayer insulating layers, and includes source/drain pillars to enhance signal isolation and storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell area is decreased to increase integration, then degree of integration is improved, but signal interference between adjacent cells increases
Solution Approach 1:
The memory device is divided into multiple independent memory cells arranged in a three-dimensional configuration. Each memory cell is segmented with isolated channel layers and gate structures, allowing high integration density while maintaining electrical isolation between adjacent cells through insulating layers, thus preventing signal interference despite close proximity
Solution Approach 2:
The memory device transitions from planar two-dimensional arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked in the vertical direction with channel layers at different heights, enabling increased integration density without increasing lateral footprint, while vertical isolation through insulating layers prevents lateral signal interference
2Productivity
If memory cell area is decreased to increase integration, then degree of integration is improved, but structural stability deteriorates
Solution Approach 1:
The memory device employs composite material structures including alternating layers of conductive gate materials, insulating materials, and semiconductor channel materials. This composite layering provides mechanical support and structural stability while enabling miniaturization, as each layer contributes specific properties that collectively maintain device integrity at reduced dimensions
Solution Approach 2:
By stacking memory cells vertically in the third dimension, the device achieves high integration without requiring further reduction in lateral dimensions. This vertical arrangement maintains adequate structural dimensions for stability while increasing capacity, avoiding the structural weaknesses that would result from excessive lateral miniaturization
3Productivity
If memory cell area is decreased to increase integration, then degree of integration is improved, but reliability of stored information deteriorates
Solution Approach 1:
Each memory cell is fully segmented with isolated channel layers, gate structures, and insulating barriers. This segmentation prevents electrical crosstalk and signal interference between adjacent cells, ensuring that miniaturization does not compromise the reliability of stored information through maintaining independent electrical boundaries for each cell
Solution Approach 2:
Insulating layers are positioned as intermediary barriers between adjacent memory cells and between different components within cells. These intermediary layers electrically isolate signals, preventing interference and maintaining data reliability despite reduced cell spacing, effectively mediating between the need for high integration and information storage reliability
Data Source
AI summary
A non-volatile memory device includes: a substrate; a gate structure including a plurality of gate electrode layers and a plurality of interlayer insulating layers, which are alternately stacked in a vertical direction on the substrate, the gate structure including a hole pattern; a data storage layer disposed inside the hole pattern; and a channel layer disposed on the data storage layer inside the hole pattern. The channel layer is disposed at each of different levels isolated from each other in the vertical direction by the plurality of interlayer insulating layers.