3D Memory Stacking Isolation Layer Access Conductors
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Solution Overview
Problem
Current 3D flash memory technologies face limitations in the number of layers that can be reliably stacked due to high aspect ratio etching challenges and intermediate structure breakage, leading to increased costs and reduced storage capacity.
Innovation Solution
A stacked structure with a memory kernel and decoding elements, where conductors are classified into bit lines and word lines, and access conductors are isolated between blocks, allowing for larger connection sizes and reduced inter-block connections, enabling more efficient stacking of 3D memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical gate structures or vertical channel structures are used to share conductors among multiple layers, then manufacturing cost is reduced, but high aspect ratio structures become hard to etch and intermediate structures may break during processing
Solution Approach 1:
The patent divides the memory structure into multiple separately patterned layers, where each layer is formed independently through its own mask and etch process. This segmentation avoids the need to etch high aspect ratio structures through the entire stack, thereby resolving the etching difficulty while maintaining cost effectiveness through standardized layer-by-layer fabrication.
Solution Approach 2:
The patent transitions from vertical conductors extending through multiple layers to horizontal conductors within each layer that connect to vertical access conductors at the periphery. This dimensional reorganization eliminates high aspect ratio etching requirements while preserving the shared conductor architecture's cost benefits.
2Reliability
If each layer of the stack is separately patterned, then manufacturing reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs universal access conductors and decoding elements that serve multiple memory layers simultaneously. These shared structures are formed once and used across multiple layers, reducing the total number of patterning steps required while maintaining the reliability benefits of separate layer processing.
Solution Approach 2:
The patent combines multiple memory layers around shared access conductors and decoding elements, allowing layers to be processed separately for reliability while sharing common structures to reduce overall manufacturing cost. The access conductors and decoding elements serve multiple layers simultaneously.
3Ease of operation
If access conductors are provided outside the kernels adjacent to memory blocks, then connection sizes can be larger and inter-block connections reduced, but device complexity increases
Solution Approach 1:
The patent extracts access conductors from the memory kernel to peripheral regions outside the memory blocks. This separation allows access conductors to be formed with larger cross-sections for better electrical connection while isolating the complex kernel structures, thereby improving connectivity without significantly increasing overall device complexity.
Data Source
AI summary
A memory can include a plurality of memory blocks, including a first block and a second block disposed over the first block. An isolation layer is disposed in this structure, between the first and second blocks to isolate the vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent the memory blocks or through regions of the blocks that only include decoding element. The access conductors are coupled to the decoding elements in the first and second blocks, and provide for connection of the memory cells to peripheral circuits.