3D Memory Substrate Bonding With Variable Isolation Heights
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and integration, particularly in three-dimensional memory cell configurations.
Innovation Solution
The semiconductor device incorporates a first substrate structure with gate electrodes and channel structures, along with a second substrate structure featuring active regions and device isolation layers of varying heights, enabling improved integration and connectivity through bonding metal layers and interconnection structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device isolation layers of uniform height are used in three-dimensional memory structures, then manufacturing process is simpler, but electrical isolation between different active regions at different heights is insufficient
Solution Approach 1:
The patent applies local quality by varying the height of device isolation layers according to specific location requirements. First device isolation layers have a first height, while second device isolation layers have a second height greater than the first height. This localized variation in isolation layer height provides enhanced electrical isolation where needed (between active regions at different heights) while maintaining simpler structure elsewhere, thus resolving the contradiction between reliability and device complexity.
2Quantity of substance
If memory cells are arranged three-dimensionally to increase storage capacity, then data storage capacity increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the three-dimensional memory structure into distinct components: first substrate structure containing plate layer and gate electrodes, second substrate structure containing active regions, and multiple device isolation layers. This segmentation allows complex 3D functionality to be achieved through coordinated simpler components, reducing overall manufacturing difficulty while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking gate electrodes vertically and creating active regions at different heights. This dimensional change increases storage capacity per unit area while the use of multiple substrate structures and varied-height isolation layers manages the associated complexity.
3Reliability
If bonding metal layers are added to connect substrate structures, then electrical connectivity between structures is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces bonding metal layers as intermediary elements between the first substrate structure and second substrate structure. These bonding metal layers provide reliable electrical connectivity while serving as a manageable interface for manufacturing processes. The bonding metal layers act as mediators that simplify the connection process between complex substrate structures, thereby improving ease of manufacture while maintaining reliable electrical connectivity.
Data Source
AI summary
A semiconductor device may include a first substrate structure including a plate layer, gate electrodes stacked on the plate layer, channel structures penetrating through the gate electrodes, and first bonding metal layers on the channel structures; and a second substrate structure connected to the first substrate structure, and including a substrate having active regions, device isolation layers in the substrate defining the active regions, circuit devices on one surface of the substrate, and second bonding metal layers connected to the first bonding metal layers, the device isolation layers including first device isolation layers and a second device isolation layer having different heights, and the active regions including first active regions spaced apart by the first device isolation layers and connected to each other by the substrate, and second active regions separated from the first active regions by the second device isolation layer.