3D Memory Structure With Isolation Etching for Dense Semiconductor Layout
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce device linewidth and increase storage density while maintaining the stability of memory structures, as existing technologies face limitations in integrating memory devices with smaller feature sizes and higher integration densities.
Innovation Solution
A method of manufacturing a semiconductor structure involving the formation of active pillars and bit lines on a base, with vertically stacked memory structures connected to the pillars, including a first and second electrode plate and dielectric layers, and an isolation layer between the word line and memory structures, allowing for 3D stacking and reduced linewidth, and ensuring electrical isolation between different transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device linewidth is reduced to increase storage density, then the integration degree of the integrated circuit is improved, but the manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D device layout to three-dimensional vertical stacking architecture. Multiple memory structures are stacked vertically along the third dimension, enabling increased storage density without further reducing the planar linewidth. This dimensional transition allows continued scaling of storage capacity while maintaining manufacturable linewidth dimensions.
Solution Approach 2:
The patent implements nested structures where word lines surround channel regions in a gate-all-around configuration, and memory structures are vertically nested on top of active pillars. This nested arrangement maximizes space utilization and increases functional integration within the same footprint, improving storage density without proportionally reducing linewidth.
2Quantity of substance
If the device linewidth is reduced to increase storage density, then the integration degree is improved, but the electrical stability and reliability between transistors deteriorate
Solution Approach 1:
The patent introduces isolation layers as intermediary structures between adjacent transistors and between the word line and memory structures. These isolation layers act as electrical mediators that prevent unwanted charge leakage and electrical interference between neighboring components, maintaining electrical stability and reliability even as devices are packed more densely in three dimensions.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the device. Isolation layers are selectively positioned in specific locations where electrical interference is most likely to occur, providing localized electrical insulation and stability enhancement without affecting the overall device performance or requiring uniform reduction of all dimensional parameters.
3Quantity of substance
If 3D stacking is implemented to reduce line width, then the memory density increases, but the device complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete functional segments stacked vertically: active pillars with channel regions, word lines, memory structures with electrode plates, and isolation layers. Each segment performs a specific function and can be independently designed and manufactured. This segmentation allows the complex 3D structure to be built through repeated stacking of standardized units, making the complexity manageable through modular assembly rather than requiring entirely custom complex structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density and stability by enabling 3D stacking of transistors and capacitor structures, reducing the critical device size, and preventing electrical failures due to connection issues between different transistors.
Implementation Method 1
etching to remove a part of the first conductive layer located on the side surface of the isolation layer
Data Source
AI summary
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base, and forming active pillars, a bit line, a word line, and memory structures. Forming the memory structures includes: providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate.