3D Memory Cell Layout With Isolation Trenches for Higher Density
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Solution Overview
Problem
Current semiconductor memory technologies face limitations in increasing storage capacity without significantly expanding footprint area, particularly in non-volatile memory solutions like FeRAM, which require innovative architectures to enhance storage density.
Innovation Solution
The development of a three-dimensional memory device architecture that stacks memory cells vertically, utilizing a multilayer stack with alternating dielectric layers and conductive layers, along with isolation structures to prevent cross-talking and improve electrical performance, allowing for increased storage capacity within a minimal footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a planar configuration, then manufacturing is simpler, but storage capacity is limited and footprint area is large
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to three-dimensional (3D) stacking architecture. Memory cells are organized in multiple tiers stacked vertically, with each tier containing memory cells arranged in rows and columns. This vertical stacking enables significant increase in storage capacity while maintaining a compact footprint area, directly resolving the contradiction between storage capacity and footprint area.
2Quantity of substance
If memory cells are stacked vertically in three dimensions, then storage density increases, but cross-talk between adjacent cells increases
Solution Approach 1:
The patent introduces intermediate structures between adjacent memory cells and tiers to prevent cross-talk. Specifically, isolation structures including dielectric materials and conductive plugs are positioned between adjacent memory cell groups and tiers. These intermediate structures act as barriers that electrically isolate adjacent cells, preventing signal interference while allowing the vertical stacking architecture to maintain high storage density.
3Reliability
If isolation structures are added between memory cell tiers, then cross-talk is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory device into distinct tiers separated by isolation structures. Each tier is independently isolated from adjacent tiers through dielectric layers and conductive plugs positioned at specific locations. This segmentation approach effectively reduces cross-talk and improves electrical performance while maintaining a modular structure that simplifies the overall manufacturing process through repeated patterning and deposition cycles.
Data Source
AI summary
A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.