3D Memory Programming With Two-Stage ISPP to Limit Overprogramming
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Solution Overview
Problem
High programming start voltage in 3D memory devices leads to overprogramming in programmed states, particularly in quaternary-level cells (QLC), resulting in inefficiencies and longer programming times.
Innovation Solution
Implementing a two-stage programming method for memory cells, including programming suppression followed by pulse programming, to manage programming voltages and reduce the likelihood of overprogramming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a high programming start voltage is applied to memory cells, then the number of programming pulses is reduced and programming time is shortened, but overprogramming occurs in programmed state P1
Solution Approach 1:
The programming process is divided into two distinct stages: a first stage applying a first voltage to bit lines to suppress programming, and a second stage applying a second voltage to enable programming. This segmentation allows the system to prevent overprogramming in the first stage while achieving efficient programming in the second stage, resolving the contradiction between programming speed and overprogramming prevention.
Solution Approach 2:
The bit line voltage is dynamically changed between two stages: initially set to a first voltage during the first stage to suppress programming and prevent overprogramming, then switched to a second voltage during the second stage to enable efficient programming. This dynamic voltage adjustment allows the system to adapt to different programming requirements at different times, achieving both speed and reliability.
2Reliability
If programming suppression is applied to prevent overprogramming, then reliability is improved, but programming efficiency is reduced
Solution Approach 1:
The programming process is segmented into two stages with different voltage applications. The first stage applies programming suppression to prevent overprogramming and ensure reliability, while the second stage removes suppression to enable efficient programming. This segmentation allows the system to achieve both reliability and efficiency by applying the appropriate voltage regime at the appropriate time.
Solution Approach 2:
Programming suppression is applied in advance during the first stage before the main programming operation. This preliminary action prevents overprogramming from occurring in the first place, ensuring reliability before the efficient programming phase begins in the second stage.
Data Source
AI summary
The present application discloses a memory programming method, a memory device, and a memory system. The method comprises: performing a plurality periods of first increment step pulse programming (ISPP) on first memory cells to be programmed to a first programmed state, comprising: at a first stage of a first period of the first ISPP, performing programming suppression to the first memory cells; and at a second stage of the first period of the first ISPP, performing pulse programming to the first memory cells. As such, the programming speed of the memory cells corresponding to the first programmed state can be reduced, and a probability of the overprogramming of the memory cells corresponding to the first programmed state can also be reduced.