3D Memory Stack Layout With Keypad-Overlapped Penetration Structure
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost and complexity of fine pattern forming technologies, necessitating the development of three-dimensional semiconductor memory devices with vertically stacked memory cells to enhance integration density.
Innovation Solution
A semiconductor memory device design featuring a peripheral circuit structure with vertically stacked conductive lines, an interconnection layer, penetration plugs, and a molding structure, where the penetration structure overlaps with a keypad to increase integration density while reducing the width of the conductive pad, allowing for precise alignment and higher integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. The stack structure with multiple conductive lines extending in the first direction and stacked in the third direction enables higher integration density by utilizing the vertical dimension, while the peripheral circuits remain integrated on the semiconductor substrate in the first region
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but manufacturing cost and complexity increase
Solution Approach 1:
By stacking conductive lines vertically in the third direction perpendicular to the substrate plane, the patent achieves higher integration density without requiring finer lateral patterning. This vertical stacking approach bypasses the need for extremely expensive fine pattern forming equipment
Solution Approach 2:
The memory device is segmented into distinct functional regions: peripheral circuits in the first region and memory cells in the second region. The stack structure separates conductive lines into multiple vertically stacked layers, allowing independent optimization of each layer without increasing overall manufacturing complexity
3Manufacturing precision
If penetration structure is positioned closer to the stack, then alignment precision improves, but risk of interference with conductive lines increases
Solution Approach 1:
The patent positions the penetration structure to vertically overlap with the first keypad in the second region, where no conductive lines are present. This local positioning strategy allows the penetration structure to be close to the stack for alignment purposes while maintaining safety distance from active conductive lines by utilizing the spatial separation between the first region (peripheral circuits) and second region (memory cells)
Data Source
AI summary
A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.