3D Memory Device With Lateral Dielectric Isolation
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Solution Overview
Problem
In three-dimensional memory devices, the formation of backside trenches for electrical isolation is time-consuming and causes substrate warpage, and existing solutions do not efficiently utilize space for word lines across multiple memory blocks.
Innovation Solution
The proposed solution eliminates backside trenches by using source-select-level and drain-select-level dielectric isolation structures and discrete source strips, allowing word lines to extend continuously between memory blocks, and utilizes source-side and drain-side select transistors to select specific memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside trenches are formed for electrical isolation, then electrical isolation between memory blocks is achieved, but manufacturing time increases and substrate warpage occurs
Solution Approach 1:
The patent divides the isolation function into two parts: source-select-level dielectric isolation structures isolate source regions between adjacent memory blocks, while drain-select-level dielectric isolation structures isolate drain regions. This segmentation eliminates the need for continuous backside trenches while maintaining electrical isolation, reducing manufacturing time and preventing substrate warpage.
Solution Approach 2:
Instead of using traditional backside trenches that extend through the substrate thickness, the patent transitions to lateral isolation structures at the source-select-level and drain-select-level. This dimensional change from vertical to lateral isolation eliminates the need for deep trench formation, significantly reducing manufacturing time and avoiding substrate warpage while maintaining electrical isolation between adjacent memory blocks.
2Reliability
If backside trenches are formed for electrical isolation, then electrical isolation between memory blocks is achieved, but device size increases
Solution Approach 1:
The isolation function is segmented into source-select-level and drain-select-level dielectric isolation structures that are laterally positioned between adjacent memory blocks. This segmentation allows isolation to be achieved at specific levels rather than requiring continuous backside trenches, reducing the overall device area while maintaining electrical isolation between memory blocks.
Solution Approach 2:
The patent transitions from vertical backside trenches to lateral dielectric isolation structures at source-select-level and drain-select-level. This dimensional change enables more efficient space utilization, allowing word lines to extend continuously between memory blocks without being interrupted by deep trenches, thereby reducing device size while maintaining electrical isolation.
3Area of stationary object
If continuous word lines extend between memory blocks, then device size is reduced, but electrical isolation between memory blocks becomes more difficult
Solution Approach 1:
The patent segments the isolation function into source-select-level dielectric isolation structures and drain-select-level dielectric isolation structures. These segmented isolation structures are positioned laterally between adjacent memory blocks, allowing word lines to extend continuously through the memory blocks while maintaining electrical isolation at the source and drain select levels.
Solution Approach 2:
The patent transitions from vertical backside trenches to lateral dielectric isolation structures at source-select-level and drain-select-level. This dimensional change enables continuous word lines to extend between memory blocks while maintaining electrical isolation, as the isolation is achieved at specific lateral positions rather than through continuous vertical trenches.
Data Source
AI summary
A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory stack structures vertically extend through the alternating stack and a respective subset of the source-select-level electrically conductive strips. A logic die may be bonded to the memory die on an opposite side of the source strips. Each source strip is electrically connected to a respective group of memory stack structures laterally surrounded by a respective source-select-level electrically conductive strip.