3D Memory Array With Lateral Access Transistors for Lower Latency
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Solution Overview
Problem
The existing three-dimensional memory devices suffer from the vertical channels and the vertical channels and the vertical channels and the vertical channels, which increase memory latency as the number of layers in NAND memory devices increases.
Innovation Solution
A three-dimensional array of unit cells is formed with vertically-extending semiconductor channels and storage devices, supported by sacrificial rails, and gate dielectrics and electrodes are patterned to create a three-dimensional array of unit cells, and gate dielectrics and electrodes are patterned to create a three-dimensional array of gate dielectrics and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in NAND memory devices increases to achieve higher memory cell density, then memory cell density increases, but the length of vertical channels increases and memory latency increases
Solution Approach 1:
The patent transitions from conventional vertical channel structures to laterally-extending semiconductor channels arranged in a three-dimensional array. By changing the channel orientation from vertical to lateral and organizing multiple channels in horizontal stacks, the design achieves high memory cell density without increasing vertical channel length, thereby reducing memory latency while maintaining high capacity
2Quantity of substance
If vertically-extending semiconductor channels are used to achieve three-dimensional memory structure, then memory cell density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs sacrificial rails that are formed in advance to provide structural support during the manufacturing process. These sacrificial rails are positioned beforehand to hold the horizontally-extending semiconductor channels in their intended three-dimensional configuration, simplifying the assembly process and enabling complex 3D structures to be manufactured with greater ease
3Loss of time
If horizontally-extending semiconductor channels are used instead of vertical channels, then memory latency is reduced, but structural support requirements increase
Solution Approach 1:
The patent introduces sacrificial rails as intermediary structures that provide temporary structural support to the horizontally-extending semiconductor channels during manufacturing. These sacrificial rails act as mediators that enable the lateral channel configuration to be maintained in three-dimensional space, after which they are removed and replaced with functional storage devices
Data Source
AI summary
A device structure includes a three-dimensional array of unit cells containing vertical stacks of the unit cells arranged along a vertical direction. Each of the unit cells includes an access field effect transistor containing a set of semiconductor material portions that includes a horizontally-extending semiconductor channel and a storage device having a first electrode electrically connected to a sidewall of the set of semiconductor material portions, a second electrode that is spaced from the access field effect transistor, and a memory layer located between the first electrode and the second electrode. Alternatively, the storage device may be a memory field effect transistor containing a ferroelectric or charge trapping gate dielectric layer.