3D Memory Page Buffer Control for Layer Compensation Reliability
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Solution Overview
Problem
Existing memory devices face challenges in maintaining reliability due to characteristic differences between memory cells formed in different layers, particularly in 3D nonvolatile memory devices with stacked word lines, which affect the core operations such as erase, program, and read operations.
Innovation Solution
The memory device employs a layer compensation circuit to independently control page buffers and word lines for each layer, adjusting operation conditions like voltage levels and application times based on layer-specific characteristics to compensate for these differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are formed in multiple stacked layers to increase capacity, then storage density is improved, but characteristic differences between layers cause reliability degradation
Solution Approach 1:
The patent implements independent control of page buffers for each layer, allowing operation conditions (voltage levels, pulse widths) to be customized according to the specific characteristics of each layer. This local optimization compensates for inter-layer variations and maintains reliable core operations across all layers while preserving high storage density.
Solution Approach 2:
The control logic circuit is segmented into multiple independent control units, each responsible for controlling page buffers of specific layers. This segmentation enables differentiated control strategies for each layer, addressing characteristic differences while maintaining the benefits of multi-layer stacking for increased capacity.
2Reliability
If independent control of page buffers for each layer is implemented, then reliability of core operations is improved, but device complexity increases
Solution Approach 1:
The control logic circuit is designed with a universal architecture that can selectively activate independent control functions based on operational requirements. During core operations, independent control is enabled for reliability; during other operations, unified control can be used, making the circuit multi-functional and reducing overall complexity.
Solution Approach 2:
The control system dynamically switches between unified control mode and independent control mode depending on the operation type. This dynamic adaptability allows the system to use independent control only when necessary for reliability, thereby managing complexity effectively while maintaining high reliability during critical core operations.
Data Source
AI summary
A memory device is provided. The memory device includes: a memory cell array including a first string provided in a first layer and a second string provided in a second layer stacked on the first layer; a page buffer circuit including a first page buffer corresponding to the first string of the first layer and a second page buffer corresponding to the second string of the second layer; and a control logic circuit configured to control the first page buffer and the second page buffer independently, in a core operation.