3D Memory Cell Layer Recess Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration density and reducing parasitic capacitance in three-dimensional memory cells.
Innovation Solution
A method for fabricating a semiconductor device involves forming a stack body with specific layers, creating openings, and recessing layers to form capping layers, liner structures, and data storage elements, which are coupled to third layer patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional memory cell structures are used, then device integration is achieved, but parasitic capacitance increases and integration density is limited
Solution Approach 1:
The memory cell structure is segmented into distinct functional layers including bit line, word line, and capacitor regions. The capacitor is divided into electrode structures with dielectric layers, separating charge storage functionality from access functionality. This segmentation reduces parasitic capacitance between adjacent conductive elements while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell layouts to three-dimensional vertically stacked structures. Multiple bit lines and word lines are stacked in the vertical direction, with capacitors positioned at different heights. This dimensional change enables higher integration density while reducing parasitic capacitance by increasing separation between conductive elements in the vertical dimension.
2Productivity
If layer thickness is reduced to increase integration density, then more cells can be stacked, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent employs atomic layer deposition (ALD) to precisely control the thickness of dielectric layers and barrier layers at the nanometer scale. By changing the deposition parameters such as precursor flow rates, temperature, and cycle numbers, the manufacturing process achieves high precision in layer thickness control, enabling integration density improvement without sacrificing manufacturing precision.
3Productivity
If complex fabrication processes are used to achieve high integration, then memory capacity increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs a unified fabrication process that forms multiple functional structures simultaneously. The same atomic layer deposition process forms barrier layers, dielectric layers, and capping layers. The same etch process creates vias and trenches for multiple purposes. This multi-functionality approach increases memory capacity while controlling fabrication process complexity by reusing process modules.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack body; forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the capping layer and an edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element that is coupled to the third layer pattern.