3D Memory Select Layer Segmentation for Reliable Cell Stacking
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices decreases as the number of stacked memory cells increases, due to increased complexity and potential defects in the stacked structure.
Innovation Solution
The semiconductor memory device incorporates a source structure, stacked conductive layers, select conductive layers, insulating layers, slit structures, and a separation insulating structure to enhance operational reliability by separating the select conductive layers and maintaining a controlled depth for the separation insulating structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of stacked memory cells is increased to improve integration degree, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the device decreases
Solution Approach 1:
The select conductive layer is divided into multiple separated regions by insulating structures, creating isolated segments that prevent defect propagation. This segmentation allows the device to maintain high integration with multiple stacked memory cells while improving reliability by containing potential failures within isolated segments rather than allowing them to affect the entire conductive layer.
2Area of stationary object
If the number of stacked memory cells is increased to improve integration degree, then the area occupied by memory cells per unit area is reduced, but the complexity of the stacked structure increases
Solution Approach 1:
The insulating structures physically divide the select conductive layer into separate segments, simplifying the overall device architecture by creating modular, isolated units. This segmentation approach reduces the complexity of the stacked structure by preventing interconnections between adjacent memory cell regions, making the device easier to manufacture and test despite having multiple stacked layers.
Solution Approach 2:
Insulating structures are strategically placed at specific locations within the stacked structure to provide local isolation where needed. This localized approach to segmentation allows the device to maintain simplicity in regions where isolation is not required while providing targeted complexity only where defect prevention is necessary, optimizing the overall device design.
3Reliability
If select conductive layers are separated to improve operational reliability, then pattern failure is reduced, but the device structure becomes more complex
Solution Approach 1:
Insulating structures serve as intermediary elements that physically separate the select conductive layer into distinct segments. These intermediary structures prevent direct electrical connections between adjacent regions, thereby reducing pattern failure and improving operational reliability. The insulating structures act as mediators that isolate potential defect sources while maintaining the overall functionality of the stacked memory device.
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.