3D Memory Layer Segmentation for Charge Confinement and Retention
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Solution Overview
Problem
As 3D memory devices increase in capacity, charge loss becomes prominent due to the spreading of trapped charges along the memory layer, impairing data retention and reducing the precision of memory cell operations.
Innovation Solution
The structure of the memory layer is modified to include sub-memory layers disconnected from each other, with portions aligned along its extending direction, and portions of the blocking and tunneling layers are removed or moved to suppress charge spreading, improving charge confinement and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory layer structure is modified to include disconnected sub-memory layers, then charge confinement and data retention are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory layer is divided into multiple disconnected sub-memory layers (first sub-memory layer and second sub-memory layer) that are separated by etching recesses. This segmentation prevents charge spreading along the memory layer while maintaining the overall memory functionality, directly addressing the charge loss problem in high-capacity 3D memory devices.
Solution Approach 2:
The patent introduces vertical dimensionality by creating recesses that extend into the memory layer, forming discrete sub-memory portions at different vertical levels. This dimensional change allows charge confinement in the vertical direction while maintaining horizontal memory operations, resolving the contradiction between capacity and charge retention.
2Reliability
If portions of blocking and tunneling layers are removed or moved, then charge spreading is suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The blocking and tunneling layers are prepared and positioned in advance during the fabrication process, with recesses formed to create discrete charge trapping regions. This preliminary structuring ensures precise charge confinement zones are established before memory operations begin, reducing the need for post-fabrication adjustments and managing precision requirements.
Solution Approach 2:
The blocking and tunneling layers are selectively removed or modified in specific local regions (at the recesses) rather than uniformly across the entire memory layer. This localized modification achieves charge confinement where needed while maintaining manufacturing feasibility through targeted processing steps.
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole (203) in a structure (202) is formed. The structure (202) includes a plurality of first layers (2021) and a plurality of second layers (2022) alternately arranged over a substrate (201). An offset between a side surface of each one of the plurality of first layers (2021) and a side surface of each one of the plurality of second layers (2022) can be formed on a sidewall of the initial channel hole (203) to form a channel hole (213). The channel hole (213) with a channel-forming structure can be formed to form a semiconductor channel (22). The channel-forming structure can include a memory layer (222) extending along a vertical direction. The plurality of second layers (2022) can then be replaced with a plurality of gate electrodes (242).