3D Memory Layer Selection via TFT Bitline Coupling
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Solution Overview
Problem
The challenge in embedded dynamic random access memory (eDRAM) is the difficulty in interconnecting multiple layers of memory cells in the back-end-of-line (BEOL) of an integrated circuit, which leads to significant area requirements for routing data lines to peripheral circuitry, especially when multiple memory cell layers are involved.
Innovation Solution
The implementation of a multi-layer DRAM device with 2D arrays of metal-insulator-metal (MIM) capacitors and thin film transistors (TFTs) allows for selective coupling of global bitlines to local bitlines through array layer select TFTs, enabling vertical integration of memory cell arrays without excessively increasing the memory device footprint, with TFTs and MIM capacitors residing within the BEOL metallization levels and FEOL FETs providing peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell layers are implemented in the BEOL, then memory density is improved, but the area required for routing data lines to peripheral circuitry increases significantly
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by implementing memory cell layers stacked in the vertical dimension. Data lines are routed vertically through the BEOL metallization levels using conductive vias, allowing multiple memory layers to share common peripheral circuitry without proportionally increasing routing area. This dimensional change enables memory density to scale with the number of layers while keeping the footprint relatively constant.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically within the same footprint, with each layer containing memory cells, local bitlines, and local wordlines. These layers are nested within a common structure that shares global bitlines and peripheral circuitry, allowing efficient use of space and reducing the area required for routing data lines to peripheral circuitry.
2Quantity of substance
If multiple memory cell layers are implemented in the BEOL, then memory density is improved, but the complexity of interconnecting the layers increases
Solution Approach 1:
The patent implements global bitlines that serve multiple memory cell layers simultaneously, allowing a single set of global bitlines to be shared across all layers. This multi-functionality reduces interconnection complexity by eliminating the need for separate global bitline sets for each layer. The peripheral circuitry also serves all layers universally, further simplifying the interconnection architecture.
Solution Approach 2:
The patent segments the bitline structure into local bitlines (layer-specific) and global bitlines (shared across layers), and similarly segments wordlines into local and global components. This segmentation allows each layer to have its own local routing while sharing common global routing resources, reducing overall interconnection complexity. The segmented architecture enables independent control of each layer while maintaining efficient shared connectivity.
Data Source
AI summary
In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.