3D Memory Device Layer Stacking and Etch Selectivity
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Solution Overview
Problem
The challenge lies in manufacturing miniaturized memory devices with 3-dimensional structures while preventing substrate deformation due to stress differences between thin films during deposition.
Innovation Solution
The method involves alternately stacking dielectric and sacrificial layers on a substrate, forming holes and openings, and using specific gases to deposit silicon oxide and silicon nitride layers, with an etchant to remove the sacrificial layers, ensuring etch selectivity and controlling the process conditions to prevent substrate deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2-dimensional memory structure is used, then manufacturing process is simple, but data processing capacity is limited
Solution Approach 1:
The patent transitions from a 2-dimensional memory structure to a 3-dimensional structure by stacking multiple layers of dielectric and sacrificial materials vertically. This dimensional change enables increased data storage capacity within the same footprint area, directly addressing the limitation of 2-D structures while managing the increased manufacturing complexity through systematic layer formation processes
2Volume of moving object
If thin films are deposited to form 3-dimensional structure, then memory device is miniaturized, but substrate deformation occurs due to stress difference
Solution Approach 1:
The patent applies preliminary anti-action by carefully selecting and controlling deposition parameters (temperature, pressure, gas flow rates) before stress-induced deformation can occur. The process conditions are pre-optimized to minimize stress differences between deposited layers, preventing substrate warpage before it happens rather than correcting it afterward
Solution Approach 2:
The patent employs parameter changes by adjusting deposition temperature (300-790°C), pressure (10-250 Torr), and gas composition during thin film formation. These parameter variations control the stress state of deposited layers, enabling miniaturization while maintaining substrate stability through precise process control
3Device complexity
If etchant is supplied to remove sacrificial layers, then 3-dimensional structure is formed, but dielectric layers may be damaged
Solution Approach 1:
The patent applies local quality by forming sacrificial layers with specific local properties (etch selectivity) that differ from the dielectric layers. The sacrificial layers are designed to be highly susceptible to the etchant while dielectric layers remain resistant, enabling selective removal of sacrificial material to form 3-D structures without damaging the dielectric components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient manufacturing of 3-dimensional memory devices, reducing volume and preventing substrate deformation, thereby enhancing the manufacturing process and device performance.
Implementation Method 1
the stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer, and the stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer
Implementation Method 2
supplying an etchant through the opening to remove the sacrificial layers, wherein the dielectric layer and the sacrificial layer may have an etch selectivity with respect to the etchant
Data Source
AI summary
Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.