3D Memory Device Layer Transfer Bonding
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Solution Overview
Problem
As integrated circuits (ICs) scale down, wire performance and power consumption become dominant issues due to increased wire lengths, which hinder the further improvement of IC performance and functionality.
Innovation Solution
The development of three-dimensional (3D) integrated circuit (IC) devices and fabrication methods, specifically using layer transfer techniques such as epitaxial layer transfer (ELTRAN) and selective etching of SiGe vs. silicon, to reduce wire lengths and improve transistor density, allowing for oxide-to-oxide and conductor-to-conductor bonding between wafers, enabling heterogeneous integration and thermal isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If 3D stacking of semiconductor devices is implemented, then wire lengths are reduced and transistor density improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by transferring multiple semiconductor wafers onto a single substrate. This dimensional change allows transistors to be positioned closer in the vertical dimension, significantly reducing wire lengths between components while organizing complex interconnections through structured transfer layers and bonding interfaces.
Solution Approach 2:
The patent divides the complex 3D integration process into manageable segments: individual wafer fabrication, selective etching of transfer layers, sequential wafer transfer, and bonding. Each wafer is processed and transferred independently, allowing complex device structures to be built through repeated application of standardized process modules rather than monolithic fabrication.
2Quantity of substance
If multiple wafers are transferred and bonded together, then transistor density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces transfer layers (such as SiGe sacrificial layers) as intermediary structures that facilitate precise wafer positioning and bonding. These intermediary layers enable alignment features and mechanical interlocking structures that maintain sub-micron positioning accuracy during the transfer and bonding processes, allowing high transistor density without compromising manufacturing precision.
Solution Approach 2:
The patent performs preliminary processing of transfer layers including selective etching, deposition of alignment features, and preparation of bonding surfaces before actual wafer transfer. These preliminary actions establish precise geometric references and chemical bonding conditions that ensure accurate positioning and reliable bonding, enabling high transistor density through controlled sequential assembly.
3Adaptability or versatility
If oxide-to-oxide and conductor-to-conductor bonding is performed, then heterogeneous integration is enabled, but process complexity increases
Solution Approach 1:
The patent employs universal bonding interfaces that can accommodate different wafer types and material compositions. The oxide-to-oxide and conductor-to-conductor bonding schemes provide standardized interface protocols that work across heterogeneous materials (silicon, SiGe, different metal interconnects), enabling versatile integration of diverse technology nodes and substrate types through a common bonding framework.
Solution Approach 2:
The patent utilizes controlled parameter changes during bonding including temperature cycling, pressure application, and atmospheric control to achieve reliable oxide-to-oxide and conductor-to-conductor bonding. By systematically adjusting these process parameters, the patent enables heterogeneous integration of different materials and structures while managing process complexity through standardized parameter sets for different bonding scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wire lengths, enhances transistor density, and improves performance and functionality of ICs by allowing for more efficient thermal management and integration of diverse technology nodes and substrate types, addressing the dominance of wire performance and power consumption issues.
Implementation Method 1
the bonding includes oxide to oxide and conductor to conductor bonding
Implementation Method 2
the bonding includes oxide to oxide and conductor to conductor bonding
Data Source
AI summary
A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.