3D Memory Semiconductor Layout for Denser Arrays and Smaller Chips
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Solution Overview
Problem
The increasing memory cell density in 3D memory devices leads to larger occupied areas by string drivers and row decoders, which can waste potential space for memory cells and increase chip size.
Innovation Solution
The layout of semiconductor structures in 3D memory devices is optimized by positioning string drivers and row decoders between page buffers, symmetrically placing row decoders on both sides of string drivers, and integrating semiconductor structures vertically to reduce overlap with memory arrays, allowing full utilization of chip space for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If string drivers and row decoders are positioned to increase memory cell density, then memory cell density is improved, but chip area occupied by peripheral circuits increases
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking, positioning string drivers and row decoders in different vertical layers above memory arrays. This dimensional change allows peripheral circuits to occupy vertical space rather than horizontal space, increasing memory cell density without proportionally increasing chip area.
Solution Approach 2:
The patent implements nested positioning where string drivers and row decoders are vertically stacked above memory arrays, with peripheral circuits nested within the vertical profile of the memory device. This nesting allows multiple functional blocks to share the same horizontal footprint, improving memory cell density while controlling overall chip area.
2Quantity of substance
If string drivers and row decoders are positioned to increase memory cell density, then memory cell density is improved, but overlap with memory arrays increases
Solution Approach 1:
The patent resolves overlap issues by moving string drivers and row decoders to different vertical dimensions above memory arrays. This vertical separation in the third dimension eliminates planar overlap while maintaining functional connectivity, allowing increased memory cell density without sacrificing overlap area.
3Reliability
If symmetric layout is used to balance signal routing, then signal integrity is improved, but metal layer usage increases
Solution Approach 1:
The patent uses vertical stacking to achieve signal routing balance in the vertical dimension rather than requiring symmetric horizontal placement. This reduces the need for extensive metal interconnect layers while maintaining signal integrity through controlled vertical routing paths between stacked components.
Data Source
AI summary
Methods, devices, and systems for managing layouts of semiconductor structures in three-dimensional (3D) memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory array in a first array region, a second memory array in a second array region, and word lines coupled to memory cells in the first memory array and memory cells in the second memory array. The second semiconductor structure includes row decoders. The first semiconductor structure and the second semiconductor structure are stacked together along a second direction perpendicular to the first direction. At least one part of the row decoders overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in a plan view perpendicular to the second direction.