3D Semiconductor Memory Cell Layout for Field Interference Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration of memory cells without relying on finer patterning technologies, which limits the reduction of memory cell size.
Innovation Solution
A three-dimensional configuration of memory cells is implemented, utilizing a stacked structure with conductive and insulating films, where memory cells share conductive films and insulating layers, allowing for increased storage capacity without requiring advanced patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase integration, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements a three-dimensional stacked structure where multiple memory cells are nested within each other vertically. Each memory cell consists of a channel region and a storage region stacked in the vertical direction, with conductive films and insulating films alternating between layers. This nesting approach allows multiple memory cells to occupy the same horizontal footprint while being differentiated by their vertical positions, thereby increasing storage capacity without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of memory cells to a three-dimensional stacked configuration. By utilizing the vertical dimension, the patent achieves higher integration density. Multiple memory cells are arranged in stacked layers, with word lines extending vertically through multiple layers to select specific memory cells. This dimensional change allows for increased storage capacity while maintaining manageable manufacturing complexity through systematic layer-by-layer construction.
2Area of moving object
If channel regions are placed closer together to reduce memory cell size, then integration density is improved, but electric field interference increases
Solution Approach 1:
The patent introduces insulating films as intermediary structures between adjacent channel regions in the vertical stacking arrangement. These insulating films act as mediators that electrically isolate the channel regions from each other, preventing direct electric field coupling while still allowing the channel regions to be positioned close together for high integration density. The insulating films provide the necessary electrical separation without requiring large horizontal spacing between channel regions.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the memory device. Specifically, insulating films with appropriate dielectric properties are placed at specific locations between channel regions to provide localized electrical isolation. This local quality approach allows for precise control of electric field distribution, enabling close spacing of channel regions while maintaining sufficient electrical isolation to prevent interference between adjacent memory cells.
Data Source
AI summary
According to one embodiment, in a semiconductor memory device, a third conductive film extends in a third direction intersecting a first direction and a second direction within a first semiconductor film. A fourth conductive film is separated from a third conductive film in the first direction. The fourth conductive film extends in the third direction within the first semiconductor film. A fifth conductive film extends in the third direction within the first semiconductor film between the third conductive film and the fourth conductive film. A reference potential is applied to the fifth conductive film. A first memory cell is provided at a position in which a first conductive film faces the first semiconductor film with a first insulating film interposed therebetween. A second memory cell is provided at a position in which a second conductive film faces the first semiconductor film with a second insulating film interposed therebetween.