3D Memory Cell Layout for Low-Power Neuromorphic Computing
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Solution Overview
Problem
Existing neuromorphic devices face challenges in integrating memory cells efficiently while reducing power consumption, as they often require significant current flow and high power usage for operations.
Innovation Solution
The semiconductor device arranges memory cells in a three-dimensional grid, storing weights corresponding to one layer of a neural network in memory cells at the same height, allowing for simultaneous activation of a portion of these cells and deactivation of others, thereby reducing current flow and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If memory cells are arranged in three-dimensional grid and weights are stored in cells at same height, then integration is improved and power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies three-dimensional stacking of memory cells in the vertical direction (third direction perpendicular to substrate) to increase storage capacity without expanding planar area. Memory cells are arranged in multiple stacks at different heights, enabling spatial optimization and reduced power consumption by activating only relevant stacks during operations.
Solution Approach 2:
The patent divides the neural network weights into multiple segments stored in different memory cell stacks at various heights. Each stack can be independently activated or deactivated, allowing selective operation of portions of the neural network to reduce power consumption while maintaining overall functionality.
2Area of stationary object
If memory cells are arranged in three-dimensional grid and weights are stored in cells at same height, then integration is improved, but device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of memory cells in the third direction to achieve three-dimensional integration. Multiple memory cell stacks are positioned at different heights above the substrate, enabling high-density storage without increasing the planar footprint, thus improving integration efficiency.
Solution Approach 2:
The patent implements nested arrangement where multiple memory cell stacks are vertically positioned within the same planar footprint. Each stack contains multiple memory cells arranged in series along the vertical direction, creating a compact nested structure that maximizes space utilization.
3Use of energy by stationary object
If current flow is minimized by selective activation, then power consumption is reduced, but operation speed may be affected
Solution Approach 1:
The patent activates only the necessary portion of memory cell stacks corresponding to the current neural network layer being processed, rather than activating all stacks simultaneously. This partial action reduces power consumption by minimizing current flow through inactive stacks while maintaining operation speed for the active portion.
Solution Approach 2:
The patent employs periodic activation of different memory cell stacks corresponding to different neural network layers. During inference operations, stacks are activated in sequence or in parallel groups, allowing power consumption to be reduced by deactivating unused stacks while maintaining overall processing throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration and reduces power consumption by minimizing current flow through bit and source lines, enabling efficient neuromorphic computing operations.
Implementation Method 1
a ferroelectric layer and a gate electrode layer surrounding the channel layer
Data Source
AI summary
A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.